Containing wafer costs while customizing CMOS
07/01/2006
In the late 1980s and early 1990s, CMOS became increasingly standardized as dimensions shrunk from 1µm to 0.8µm, then from 0.6µm to 0.5µm, and then <0.35µm. At these technology generations, CMOS for high performance CPUs and CMOS for low power, battery-operated electronics did not differ much. But as CMOS technology has progressed, it has also become increasingly more “customized” to the product application and design approach used to integrate analog/RF and to reduce power.
At the 0.25µm generation, processes for different applications began to diverge substantially. High-performance processes required a high-drive current (Idrive) achieved by lowering threshold (Vt) and increasing leakage. Low power processes required low leakage, which is achieved by higher Vt and a consequent loss of Idrive. Development engineers learned to “tune” the process to the application by trading Idrive for leakage current. In round numbers, a 40mV reduction in Vt resulted in a 15% increase in Idrive and a 10× increase in leakage. Fab engineers also learned the importance of the Ion−Ioff curve. Ion = Idrive, and Ioff is the leakage current in the off state. Moving up and down the Ion−Ioff curve is easily accomplished by changing the pocket implant or the Vt adjust implant. However, moving the Ion−Ioff curve requires increasing inversion layer capacitance (Cinv ), or channel mobility.
At the 130nm node, system-on-chip (SoC) integration of analog and RF functions started to become important, especially in wireless products. While SoC integration of digital functions is as old as the industry itself, analog and RF integration in digital CMOS presented an increasing number of challenges.
Analog and RF functions have historically been implemented using different process technologies. Analog functions have been implemented using high-voltage CMOS that lags the state-of-the-art in terms of feature size, but contain special “analog” components/features, such as high-resolution capacitors and resistors, inductors, varactors, and isolation. RF functions have historically been implemented in BiCMOS processes. When integrating analog, RF, and digital functions onto a single chip, as in TI’s recently introduced single-chip cell phone, these functions need to be implemented in a CMOS process that costs no more to produce than standard digital CMOS. This requires changes that make the flow unique to the class of products being designed. SoC integration of analog and RF functions in digital CMOS further accelerated the need to customize CMOS technology to the application.
Integration of analog/RF functions onto digital chips also requires changes to product architecture and circuit techniques. TI’s digital radio processor is a good example of innovative architecture and circuit techniques that are required.
At the 65nm node, the issue of power rose to crisis proportions. For low-power, battery-operated products, it was no longer possible for fab engineers to hold subthreshold leakage current to the historical level of 10pA/µm of transistor width. Moreover, gate-oxide tunnel current and gate-induced diode leakage (GIDL) began to contribute significantly to overall CMOS standby power. As a result, new design techniques were developed to reduce standby leakage power, and these require changes to the fab process that are customized to the design approach.
For example, a commonly used technique is to apply body bias in standby to increase Vt and reduce subthreshold leakage, but increasing body bias increases GIDL. For that reason, the 65nm process was engineered to hold all sources of leakage to acceptable levels under a variety of supply voltage and body-bias conditions.
Today, as opposed to the 1980s, there is no such thing as standard commodity CMOS. Companies increasingly customize their CMOS processes to match product strategy, i.e., high performance vs. low power and cost requirements; system partitioning strategy, i.e., SoC integration vs. system-in-package; and design strategy.
Increasingly, companies will attempt to differentiate their products with their own custom CMOS flow, and the number of CMOS process technologies will continue to increase and diversify. The challenge for fab engineers will be to accommodate this diversification without increasing wafer cost.
Contact Dennis Buss, VP, silicon technology development, at TI, 13560 North Central Expressway, MS 3735, Dallas, TX 75243; ph 972/927-4076, e-mail [email protected].
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Dennis Buss
Texas Instruments, Dallas, Texas