Targeting 45nm with improved SiON films and extended gate dielectrics
07/01/2006
Silicon oxynitride gate-stack dielectrics are reaching limits for use beyond 65nm technology. But replacing them with high-k materials-which would enable higher current when the transistor is on and lower leakage when it is off-presents significant implementation challenges. Therefore, IC manufacturers are developing processes to extend the use of SiON films for the 45nm mode.
Researchers are working through high-k challenges such as thermal instability, air sensitivity, and etch profile control. Charge trapped in the film and at the interfaces shifts the transistor threshold voltage and degrades transistor performance, and long-term reliability tests established for silicon oxide and oxynitride must be re-established for high-k materials. If high-k implementation experiences severe yield or reliability problems, the financial damage could be significant.
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To avoid these risks, semiconductor manufacturers delayed high-k introduction from 65nm to 45nm. Strain and channel engineering are providing the needed performance improvements without significant scaling of the gate dielectric. Now, manufacturers are considering extending oxynitride gate dielectrics for 45nm as well.
Oxynitride gate stack
Manufacturers are finding that the present level of oxynitride performance is not the only alternative to high k. They are considering improving the nitridation and anneal processes, integrating the entire gate-stack formation process on a single system, and reducing polysilicon gate-carrier depletion. The focus for improvement is not on dramatic reductions in dielectric thickness. Rather, designers are looking for improvements in on-state transistor current (Ion), gate-leakage reduction (Jg), and dielectric reliability, typically measured in negative bias temperature instability (NBTI). Dielectric thickness is commonly expressed as the equivalent oxide thickness (EOT), the thickness of silicon oxide that would produce the equivalent capacitance.
Typically, oxynitride gate dielectric is formed as follows. After pre-gate wet clean, a base oxide is formed using radical oxidation. Next, a nitrogen plasma is used to nitridate the base oxide. The film is annealed at high temperature to improve the bonding within the oxynitride and improve the interface quality. Finally, polysilicon is deposited on the wafer to seal the finished gate dielectric, which prevents any additional thickening in the ambient environment. Other schemes are being investigated for performance improvements [1, 2].
Nitrogen profile
The nitrogen profile is one focus for providing improved gate-dielectric performance. The optimal nitrogen profile includes a high nitrogen concentration within the film but little nitrogen penetrating through the base oxide to the lower interface with the transistor channel. A few percent of nitrogen at the interface has been shown to reduce leakage [3], but more nitrogen leads to interface charge traps. These traps scatter current carriers in the channel, which degrades Ion.
To form the ideal nitrogen profile, low energy nitrogen ions must be produced. Continuous wave (CW) RF sources can produce high densities of nitrogen ions, but the ion energy is only high enough to penetrate through base oxides that are 12-14Å thick. For these thinner base oxides, a pulsed RF source is required. Figure 1 (see p. 40) shows the ion energy distribution for CW and pulsed RF sources over a range of duty cycles. As the duty cycle decreases, the ion energy distribution shifts to lower kinetic energy. Duty cycles as low as 2% will result in ion energies of only a few electron volts, which is comparable to the energy of a chemical bond.
Low energy ion nitridation from a pulsed RF source has shown clear performance benefits. Figure 2 shows the thickness-normalized maximum current-carrier mobility vs. gate-leakage reduction relative to silicon oxide. Higher carrier mobility leads to increased Ion. In Fig. 2, it can be seen that mobility degrades as gate leakage is reduced and is due to increasing nitrogen in the film that reduces leakage at the cost of mobility. However, a pulsed RF source provided improved carrier mobility for both nMOS and pMOS relative to a CW RF source. By reducing the nitrogen at the channel interface, the interface trap density decreases, allowing current to flow more freely through the channel. Reliability improvements have also been observed [4, 5].
 Figure 2. Thickness-normalized current-carrier mobility as a function of gate-leakage reduction relative to silicon oxide for a) nMOS and b) pMOS. |
Once nitrogen is in the film, high temperatures can improve the chemical bonding in the film and anneal away interface traps. The gases used during the anneal must be oxidizing to avoid damage to the dielectric, but the degree of oxidation can be varied for optimal device performance. Re-oxidation, especially at the dielectric channel interface, can improve both the interface quality and carrier mobility. However, further oxidation simply leads to thickening of the film and lower capacitance. Our data (Fig. 3) reveals the strong dependence of oxidation on Ion for nMOS. Further tuning of the anneal process has produced ~4% improvement in nMOS Ion.
Another reason to limit oxidation during the anneal is to enable the formation of thinner gate dielectrics. Some manufacturers would rather trade thinning for other performance improvements. One can reduce the oxidation that occurs during the anneal and then increase the base oxide thickness. A thicker base oxide eases constraints that designers face. Using the same nitridation process with a thicker base oxide will result in less nitrogen penetration to the channel interface, which results in higher Ion and improved reliability at the same final dielectric thickness. Alternatively, more nitrogen can be incorporated into the film, which will reduce gate leakage for the same Ion.
Exposure of the wafers to air also thickens the gate dielectric. All of the process steps, including depositing the polysilicon electrode, integrated onto a single system permit the entire gate stack to form without breaking vacuum. Figure 4 shows nMOS transistor data for fully integrated and fully interrupted processing for gate dielectrics with the same range of nitrogen dose. The distribution is shifted by ~1Å, and manufacturers have found a similar effect [6]. Eliminating this thickening permits thinner dielectrics, or a thicker base oxide can be used to achieve the same final dielectric thickness with additional performance benefits.
The gate electrode
Another place to look for improvements is at the gate electrode. Polysilicon gate electrodes have current-carrier densities at the dielectric interface under inversion that are low compared to that of a metal. This results in a lower effective capacitance, which is commonly converted to and expressed as a thickness, Tox_inv. Under optimized conditions, poly depletion can be reduced to 4Å, but no less.
One approach is to increase the carrier density at the interface with a more thorough activation of the available dopant atoms. Laser annealing is being investigated for poly-gate dopant activation [Editor’s note: see “Optimizing gate dielectrics using laser-spike annealing” on p. 47.] Lasers can anneal the wafer very near the silicon melt temperature. At these temperatures, the carrier concentration will be ~2× higher than with conventional RTA. Figure 5 shows an increase in capacitance corresponding to ~1Å of poly depletion reduction. Electrically, the films appear to be 1Å thinner with laser annealing after ploy doping and implant.
 Figure 5. Capacitance-voltage curves for a MOS capacitor that received a conventional RTP anneal and a MOS capacitor that received both RTP and laser anneal. |
Replacing polysilicon with metal for the gate electrode would eliminate poly depletion entirely as metals have a much higher current-carrier density, but they also have their own problems. Foremost is that the electrode workfunction must be matched to the device type. For bulk CMOS, pMOS requires a high workfunction metal, while nMOS requires a low one. Some metals can be easily oxidized or suffer other thermal degradation at typical semiconductor processing temperatures.
Manufacturers evaluating various metals are also evaluating multiple deposition techniques. PVD is the obvious first choice because it can be used to deposit most of the metals in the periodic table. Deposition of alloys is also straightforward, but PVD can lead to thinning of the gate dielectric. PVD can also cause charge build-up in the gate dielectric that will lead to shifts and instability of the transistor threshold voltage. Finally, PVD deposition results in high charge-trap density at the interface of the gate dielectric with the channel, which reduces current through the transistor, as is shown in Fig. 6.
 Figure 6. The channel interface trap density (Dit) comparison between the new PVD approach and a series of ALD/conventional PVD runs with different ALD thicknesses. |
Atomic layer deposition (ALD) may provide a solution to the PVD damage problem. This technique uses gentle, self-limiting process conditions that deposit a metal film one layer at a time. ALD eliminates gate-dielectric thinning and charge build-up, and results in a low level of interface traps. Channel interface trap densities (Dit) of ~10×1010cm2/eV can be achieved with ALD (Fig. 6). Furthermore, a thin ALD layer of ~25Å can protect the gate dielectric from a subsequent conventional PVD process.
Laser annealing and a metal gate would ease the limitations imposed by poly depletion, which provide potential trade-offs similar to those offered by gate-dielectric improvements. Manufacturers would have their choice. They could keep the dielectric the same thickness and reap the benefits of increased capacitance, which would lead to more control over the gate on- and off-states. Or they could thicken the gate dielectric, which would yield lower gate leakage by as much as 100× and reduce the penetration of nitrogen to the interface with the channel to increase Ion and improve reliability.
Conclusion
Improvements to the silicon-oxynitride dielectric and reductions in gate-electrode depletion will give manufacturers more process space to reach their 45nm targets. While some additional scaling over 65nm will be possible, many manufacturers will choose to trade this for improvements to increase Ion and improved reliability, while gate leakage is reduced. These improvements will give manufacturers more time to develop high-k solutions before taking the high-k gamble.
Acknowledgments
Co-authors of this paper include Peijun Ding, Suraj Rengarajan, Yi Ma, and Thai Cheng Chua.
References
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4. A. Veloso, F.N. Cubaynes, A. Rothschild, S. Mertens, R. Degraeve, R. O’Conner, et al., “Ultra-thin Oxynitride Gate Dielectrics by Pulsed-RF DPN for 65nm General Purpose CMOS Applications,” Proc. ESSDERC, 239, 2003.
5. P.A. Kraus, K. Ahmed, T.C. Chua, M. Ershov, H. Karbasi, C.S. Olsen, et al., “Low-energy Nitrogen Plasmas for 65nm Node Oxynitride Gate Dielectrics: A Correlation of Plasma Characteristics and Device Parameters,” Proc. VLSI Symposium, 143, 2003.
6. S.J. Chang, S.Y. Wu, C.L. Chen, T.L. Lee, Y.M. Lin, Y.S. Tsai, et al., “An Integrated Gate-stack Process for Sub-90nm CMOS Technology,” Extended Abstracts of the 2003 International Conference on Solid State Devices and Materials, Tokyo, p. 460, 2003.
For more information, contact Kevin L. Cunningham at Applied Materials, 974 E Arques Ave., M/S 81250, Sunnyvale, CA 94085; e-mail [email protected].