Optimizing gate dielectrics using laser-spike annealing
07/01/2006
For the past several years, the need for advanced gate-stack materials has been listed by Sematech as one of the top technical challenges faced by the semiconductor industry [1]. These new materials will help reduce gate current leakage. However, with today’s high-end CMOS devices that typically feature gate dielectrics made up of many different layers, continued evolution beyond the 90nm technology node is expected to be driven by fundamental changes not only in MOSFET gate-stack materials, but also in device structures and processing techniques. One of these process technologies is laser-spike annealing (LSA).
To minimize off-state gate leakage, chipmakers must optimize gate dielectrics, which are critical to the continued proliferation of IC transistors. New IC gate materials such as high-k dielectrics, which are expected to be implemented near the end of the 45nm technology node or at the 32nm node, can help reduce gate-current leakage. However, they also pose new process challenges. One process innovation that is proving effective in achieving gate-leakage abatement is the use of laser-spike annealing (LSA), which improves poly depletion and thus electrically extends the life of oxynitride dielectrics.
Polysilicon gate annealing
A typical multilayer gate stack involves a succession of process steps, each of which is essential to optimal IC performance, starting with a pre-clean of the substrate surface. Following this step, the gate dielectric is grown. This gate can be oxide, oxynitride, or a sandwich of many different dielectric materials. The key here is that, as devices shrink, this dielectric gets thinner.
High-k materials, due to their higher dielectric properties, can be thicker and less prone to leakage, thus easing the processing constraints created by ultra-thin oxynitrides. The gate-oxide layer is the most critical part of the device. If it is not well formed-i.e., if the thickness, uniformity, and composition are substandard-then there will be excessive leakage across the gate when voltage is applied. Following this step is the polysilicon layer, and finally, the gate metal layer is added, if needed, to complete the stack.
One of the keys to leakage abatement is poly depletion optimization using an annealing process to more fully activate dopants in the poly layer, thus causing extension of gate electrical thickness. Rapid thermal annealing/processing (RTA or RTP), the de facto thermal-processing standard for the past two decades, cannot accommodate the stringent annealing temperature/time requirements (millisecond heating at upwards of 1350°C) associated with sub-65nm devices. Other approaches, such as flash lamp annealing, can meet time and temperature requirements, but have a key drawback.
These approaches cannot heat the wafer surface uniformly, requiring the use of extensive tiling, or dummification, where dummy gates are inserted onto the wafer to create a uniform pattern density or reflectivity to aid annealing. This adds cost and complexity to the process. In addition, when the entire wafer surface is subjected to the sudden thermal load of the flash, severe warping occurs, creating additional manufacturing challenges.
Other millisecond-annealing technologies based on short wavelength radiation suffer from major pattern-dependency issues and require additional, yield-limiting steps-specifically, the use of tiles or the addition of an absorber film. Deposited at >500°C for best absorbance, the film causes solid-phase epitaxial growth, ultimately leading to retention of end-of-range damage and excessive junction leakage. For very fine-geometry devices, where gate dielectrics are minimally thin, dry-etch removal of the blanket film has led to gate-dielectric degradation and, ultimately, reliability and lifetime issues. This is a critical drawback because these gate-integrity issues cannot be detected from parametric testing and only show up later during device life testing.
LSA, by nature of its construct, minimizes pattern-density effects. LSA scans a long, narrow beam from a long-wavelength laser across the wafer surface to create a small, localized hot spot with a millisecond or shorter dwell time. Since only a thin layer at the top surface is heated and the bulk of the wafer remains cool, the surface temperature falls almost as fast as it rises. The high peak temperature produces high dopant activation, as might be expected from solid solubility considerations, and the short dwell time leads to minimal dopant diffusion, as required for the 65nm technology node and beyond. The processed region can be localized to specific areas on the wafer without affecting surrounding areas.
Reducing poly depletion
For deep-submicron technologies, inadequate dopant activation in the polysilicon gate can result in carrier depletion at the polysilicon oxide interface, degrading MOSFET performance. A high annealing temperature is required to maximize dopant activation in the gate. If conventional RTP spike annealing is used, a high annealing temperature will lead to excessive diffusion of the source/drain and source/drain-extension implants. On the other hand, this diffusion is minimized by employing LSA, whose high temperatures and short time scale allow high activation of the gate dopant. The increased gate activation achieved using LSA results in significant reduction in the effective gate-dielectric thickness.
 Gate capacitance of an a) nMOSFET and a b) pMOSFET. The poly depletion improvement associated with LSA was estimated at 0.1nm. [2] |
A recent paper [2] compared Ion/Ioff (i.e., drive current) of MOSFETs annealed by flash lamps and LSA. In both nMOSFETs and pMOSFETs, devices processed by LSA exhibited a 10% larger drain current, a performance enhancement directly attributed to improved gate depletion and reduced parasitic resistance. A 0.1nm reduction in effective gate-dielectric thickness for both MOSFET types was achieved with resistivity improvement of 20-30% (see figure).
Process optimization beyond poly depletion
LSAs have shown significantly enhanced transistor performance compared to both conventional spike annealing and flash annealing at successive optimization steps. The most basic approach is simply to add LSA to a baseline process typically employing RTP. This additional step improves polysilicon depletion-typically by an additional angstrom, with a resulting increase in electrical performance.
A second approach is to optimize the source/drain design to take advantage of the improved drive-current-to-off-current ratio (Ion/Ioff), thus enhancing Ioff for the same Ion. Third, one can lower the RTP temperature to achieve less diffusion and, therefore, reduce source/drain extension overlap. This provides further Ioff enhancement.
The most advanced step is to re-engineer the halo, extension, and source/drain implant profiles to take full advantage of the nearly diffusionless, high activation that using LSA-only annealing enables. To date, a number of major companies have published papers reporting positive results that prove the effectiveness of LSA, both in combination with RTP and as a full replacement for RTP.
Conclusion
Millisecond LSA not only provides advantages in the formation of ultrashallow junctions for advanced devices, but also assists in the demanding process of gate-dielectric formation. Perhaps it can provide some breathing room for device manufacturers by postponing broad adoption/implementation of difficult high-k dielectrics.
References
1. http://www.sematech.org/.
2. K. Adachi, et al., “Issues and Optimization of Millisecond Anneal Process for 45nm Node and Beyond,” 2005 Symposium on VLSI Technology Digest of Technical Papers.
Babak Adibi received his bachelors, masters, and PhD degrees in physics from Imperial College of London and U. of Surrey, England, and is VP of laser processing products at Ultratech Inc., 3050 Zanker Rd., San Jose, CA 95134; ph 408/321-8835, e-mail [email protected].