Combining seed layers enables the use of HAR copper interconnects
07/01/2006
The lower resistivity of copper vs. aluminum facilitates denser and faster ULSI devices with on-chip copper interconnects. However, the shrinking dimensions with each new technology generation rapidly increase the RC delays of the copper interconnect, now equal to or exceeding that of transistor delays. Also, because of the inherent limitations of physical vapor deposition (PVD) seed layers, the industry has had to maintain relatively low aspect ratios (LARs), in which the cross-section of the lines decreases as the square of the scale factor. As a result, copper interconnects will suffer rapid increases in line resistance, RC delays, signal loss, power dissipation, heating, and thermal stress. However, these shortcomings can be mitigated by using high-aspect ratio (HAR) copper interconnects.
This article describes a combination of a chemical vapor deposition (CVD)-or its atomic-layer deposition (ALD) variant-seed layer and a PVD seed layer, which enables the use of HAR interconnects. The combined seed layer provides fully continuous step coverage inside HAR openings, while maintaining sufficient thickness on the field for electroplating, with minimal or no top corner overhangs [1-6]. The combination seed layers facilitate consistent and reliable void-free filling of HAR trenches and vias (i.e., AR ≥10:1) that will enable the industry to realize the benefits of HAR interconnects.
The recent International Technology Roadmap for Semiconductors (ITRS) calls for copper interconnects to have LARs in the range of ~1.7:1 to 2.3:1. Using such LARs implies shrinking the heights of lines by the same scale factor used for shrinking their widths. As a result, the cross-sections of lines will decrease as the square of the scale factor, and copper interconnects will suffer rapid increases in line resistance, RC delay, signal loss, power dissipation, heating, and thermal stress. The main reason for utilizing LAR copper interconnects is an inability to provide continuous coverage inside HAR openings using PVD seed layers.
Line resistivity increases exponentially below linewidths of ~1000Å because of electron scattering at surfaces and grain boundaries, leading to increased RC delays. However, simulations [7, 8] indicate that doubling the interconnect AR can reduce RC delay by ~30-50%. Notably, this promises more of a reduction in RC delay than can be achieved using ultra-low-k (ULK) dielectrics. Additional benefits of doubling AR are: a) cutting power dissipation and heating of lines by at least 50%; b) decreasing capacitive noise coupling between adjacent metallization levels by ≥50%; c) reducing signal degradation; d) minimizing the number of metallization levels; and e) simplifying CMP control by allowing 2× thinning (acceptable variation window).
 Figure 1. Surface/volume ratio depends on AR. |
Figure 1 shows the effect of AR on the ratio A/V of surface area (A) to volume (V) in copper lines. Electron scattering at the surface of the line is proportional to A/V. Thus, for a given linewidth w, A/V decreases by increasing the line height h (i.e., by increasing AR). So increasing the AR of a line from 1:1 to 4:1 (using the same linewidth w), decreases A/V, and hence, electron scattering at the surface by 37%. A recent article by G. Alers et al. [9] indicates that, due entirely to a reduction of surface scattering, the copper resistivity of 65nm wide lines can be reduced by 30% by using a line depth of 150nm instead of a line depth of 30nm.
While there might be a justification for maintaining a LAR for lines (to minimize intralevel capacitance but not RC), there is no such justification for vias because LAR vias increase interlevel capacitance between adjacent metallization levels, thereby increasing RC delays and capacitive noise coupling. Furthermore, interlevel capacitance is inversely proportional to h [10] and, hence, to AR for a given w. As a side note, interlevel capacitance increases by 41% for diagonal (45°) routing of interconnect lines in adjacent metallization levels (i.e., X-architecture). This is due to the increased overlap area (from w2 to 21/2·w2) of crossing lines in adjacent levels. Finally, thermal stress in copper lines and associated stress-induced voids (SIV) decrease exponentially (as h-2.7) with increasing h [11, 12]. For example, increasing h (or AR) by a factor of 4 (using the same w) decreases line thermal stress and SIV susceptibility (or incidence rate) by a factor of 40.
Despite the above considerations, the industry has retained the same LAR interconnects over the last several technology nodes and appears determined to keep them as low for the next several technology nodes. In the author’s view, the main reason for doing so is an inability of PVD seed layers to provide continuous coverage inside HAR openings [13-15].
Problems with conventional seed-layer technology
PVD seed layer. In general, due to the directional (line-of-sight) character of PVD technology, PVD seed layers have poor step coverage on sidewalls of HAR openings. The thickness of a PVD seed layer at mid-to-lower sidewalls is only ~3-8% of its thickness on the field surrounding the openings. Consider that a typical PVD seed layer is relatively thick on the field (800-1200Å), but is very thin (≤30-100Å), or discontinuous, at the lower sidewalls of narrow openings (i.e., openings having a width in a range of ~0.05-0.13µm). In addition, PVD seed layer step coverage is even poorer than that described above for openings with sidewalls having uneven surfaces and/or negative slopes. Negative slopes are often found on concave profiles or at localized nooks, crevices, and recesses created by undercutting (or overetching) of dielectric layers.
 Figure 2. Schematic filling voids and SIV precursors. |
The problem of negative slopes is particularly acute for openings in dual-damascene structures that are etched in stacks of different dielectric layers. Figure 2 shows a schematic dual-damascene opening having negative slopes created by undercutting a dielectric etch-stop (or barrier) layer. The difficulty in providing step coverage in such openings has been widely reported. Son et al. [14] reported undercutting in a SiNX layer having negative sloped sidewalls and discontinuous PVD seed layer coverage.
The problem with seed-layer discontinuities is that during electrofilling they lead to electrofilling voids and/or SIV precursors, which both occur at seed-layer discontinuities because the exposed Ta barrier reacts with the plating electrolyte to form a tantalum oxide and/or a tantalum hydroxide film. This passive film produces electrofilling voids (over larger seed-layer discontinuities) or void precursors (over smaller discontinuities).
Void precursors are a major cause of SIVs, and a significant cause of electromigration (EM). Further, although electrofilled Cu might bridge small seed-layer discontinuities, it has poor or no adhesion to the underlying tantalum oxide and/or tantalum hydroxide passive film. This information is important because studies by KLA-Tencor and Texas Instruments [16, 17] indicate that electrofilling voids and void precursors are the major cause of poor reliability and low yields in copper interconnects, constituting >70% of dual-damascene copper interconnect failures. Additionally, electrofilling micro-voids near the bottom sidewalls coalesce (under thermal and/or electrical stresses) into larger voids that result in via pulls [18].
Another problem associated with small discontinuities in Cu PVD seed layers is that they tend to expand rapidly by corrosion of the seed layer in a plating electrolyte. Such corrosion is accelerated by the galvanic effect of simultaneously exposed seed and barrier layers, and by stress at the barrier/seed interface. To minimize seed layer corrosion, most users initiate “hot” plating by applying plating current on the first contact of a wafer with the plating electrolyte. Unfortunately, this procedure leaves surface contamination and native copper-oxide on the Cu seed layer, resulting in defects and poor adhesion of the plated copper to the seed layer. This problem does not occur for a fully continuous seed layer because it corrodes rather slowly (≤10Å/min) inside openings. This allows a reasonable idle period (during which there is no applied current) for activation by etching of the native copper-oxide in the acidic electrolyte.
Other seed layers. A single seed layer deposited by a CVD (or its ALD variant) method, an electroless (EL) method, or an electroplating (electrochemical deposition or ECD) method provides fully continuous coverage inside HAR openings. However, such a single seed layer tends to be too thick on the sidewalls and/or too thin on the field. A seed layer that is too thin on the field leads to large initial current variations across the wafer during electrofilling. This too-thin layer may be dissolved by bipolar dissolution [19] and is prone to mechanical wiping at edge contacts during electrofilling.
A highly conformal seed layer that is too thick on the sidewalls tends to pinch off the openings, resulting in electrofilling seam-voids. Other drawbacks of such a single seed layer are: a) a slow deposition rate (in particular for seed layers deposited using ALD); b) poor adhesion and nucleation of the seed layer on the barrier layer due to formation of a deleterious interfacial film and/or contamination (in particular for seed layers deposited using an EL, ECD, or a CVD method); c) high impurity and resistivity levels; and d) seed layers (deposited using EL or ECD methods) that require added specialized equipment.
“Repaired” seed layers have been proposed, in which a relatively thin (and discontinuous) PVD seed layer is repaired by ECD, or EL of an additional repair Cu seed layer [20-25]. The plated seed layer is alleged to repair discontinuities of the PVD seed layer inside the openings. However, these repaired seed layers are problematic since they still produce SIV-precursors due to formation of a tantalum oxide (and/or hydroxide) passive film at exposed barrier sites, thereby impairing adhesion of the repair seed layer to the Ta barrier. Also, the plated repair seed layer must have a certain minimal thickness on the sidewalls to bridge discontinuities of the PVD seed layer.
For reliable bridging, the minimal thickness of the plated repair seed layer on the sidewalls should be at least 200-300Å. The problem is that such a thickness might pinch off narrow openings (≤1000Å). At the same time, the repaired seed layer might be too thin on the field, thus impairing wafer surface conduction. Other drawbacks of repaired seed layers are: a) high impurity and resistivity levels; b) hydrogen evolution (blistering); c) erratic and hard-to-control processes (particularly EL); d) low throughput due to a slow deposition rate; e) a high via resistance [25]; and f) the need for specialized hardware.
Recently, there has been a push to reduce the thickness of the barrier and seed layers. While this is justified for the barrier layer, it is unjustified and counterproductive for the seed layer. The rationale for a very thin PVD seed layer is to reduce overhangs at the top corners. The rationale for a very thin ALD seed layer is to increase throughput, minimize volume fraction of Ru or other high-resistivity metals, and reduce cost. Equipment vendors are developing new ECD tools that supposedly can electroplate uniformly over a very thin (50-300Å) and highly resistive seed layer of Cu or Ru. However, such tools may not be as economical or reliable as conventional tools. As demonstrated below, combination seed layers enable the continued use of conventional ECD tools and make the need for exotic tools unnecessary.
Combination seed layers
An optimal seed layer can be obtained by combining a relatively thick (~500-1500Å) PVD seed layer and a relatively thin (~25-100Å) CVD (particularly its ALD variant) seed layer [1-6]. The thin CVD or ALD seed layer provides fully continuous sidewall and bottom coverage without sealing or pinching off the openings, and the thick PVD seed layer provides sufficient surface conduction to enable uniform plating across the wafer.
Minimization or elimination of PVD seed layer overhangs is straightforward when the PVD seed layer is not required to provide good sidewall coverage. Under such conditions, a relatively thick PVD seed layer can be deposited on the field with negligible overhangs. The combination seed layers enable uniform plating across the wafer, robust and consistent void-free filling of the most demanding HAR openings, greatly improved reliability (i.e., reduced SIV and EM) and yields, and extended use of conventional ECD tools. They offer similar cost and throughput to that of a single PVD seed layer and are fully adequate for the current and foreseeable technology nodes. Using such seed layers, extreme HAR features can be electrofilled without voids. For example, trenches with a width of only ~500Å (at bottom), depth of 1.4µm, and AR of 28:1 were electrofilled with copper without voids [2, 3].
 Figure 3. PVD/CVD seed layers: ~450Å (including barrier) on sidewalls and ~1000Å on the field. Trenches: ~0.13µm wide (bottom); 1.4µm deep; AR ≈ 10.8:1; tilt = 30°. |
Figures 3 and 4 demonstrate examples of combined seed layers. Figure 3 shows combination PVD/CVD seed layers deposited over 0.13µm trenches with a HAR of 10.8:1. The combined thickness of the seed layers and barrier layer is ~450Å on the bottom and sidewalls and ~1000Å on the field. The combination seed layer is fully continuous on the sidewalls and bottom, and its thickness on the field is sufficient for uniform plating. No overhangs are seen at the top corners.
Figure 4 shows another combination PVD/CVD seed layer deposited over 0.10µm trenches with a HAR of 14:1. The combined thickness (including the barrier layer) is ~1900Å on the field, while it is only ~450Å on the bottom and sidewalls. The CVD seed layer provides excellent uniform bottom and sidewall coverage without sealing the openings, while the thick PVD seed layer provides more than adequate surface conduction on the field. No appreciable overhangs of the thick PVD seed layer are seen at the top corners. The ample thickness of the PVD seed layer shown in Fig. 4 is only for demonstration of the capability to obtain a very thick PVD seed layer with negligible overhangs. The PVD Cu seed layers in these experiments were sputter-deposited in a simple sputtering machine without bias, collimation, or metal ionization. Future combination seed layers would most likely utilize a much thinner ALD seed layer with a relatively thick PVD seed layer. Indeed, a recent publication by ASM International advocates depositing a thin ALD Cu seed layer over a relatively thick PVD Cu seed layer [26]. Another recent publication by Applied Materials advocates depositing a PVD Cu seed layer over an ALD Ru seed layer [27].
From an electroplater’s point of view, sufficient thickness and low resistivity of the seed layer on the field are essential for uniform (edge-to-center) current distribution across the wafer during the initial stage of plating. A uniform current distribution is required to minimize the notorious “terminal effect” (i.e., a thickness nonuniformity) and more importantly ensures edge-to-center void-free superfilling of the narrowest features, whereas the void-free superfilling mechanism is effective only within a narrow range of current density.
During the initial stage of plating, if the current density drops significantly from edge-to-center, then certain radii of the wafer might fall outside the effective superfilling current density range, resulting in filling voids of the narrowest features at these radii. For example, for a 600Å thick Cu seed layer on 200mm wafers and for a 1200Å thick Cu seed layer on 300mm wafers, the initial plating current density variation (edge-to-center) is >60% [28]. The variation is much larger for thinner and/or higher resistivity metal seeds.
While feature size scales down with every technology node, the wafer diameter stays the same (or even increases, e.g., from 200mm to 300mm). Therefore, the wafer’s surface conduction (i.e., seed-layer thickness divided by its resistivity) should, at the very least, be maintained constant with new technology nodes. This means that seed-layer thickness on the field should not be reduced and seed-layer resistivity should not be increased by replacing the copper seed layer with other metals of much higher resistivity (such as Ru).
Beyond these requirements, an adequate seed layer should: a) provide fully continuous coverage on the sidewalls and bottom of the openings, yet be thin enough inside the openings to leave sufficient room for electrofilling; b) have minimal or no overhangs on the top corners; c) not be less noble than copper in the plating electrolyte, which would otherwise lead to its spontaneous displacement by copper, thus impairing adhesion; d) not develop spontaneous oxide and/or hydroxide passive film in the plating electrolyte (e.g., Ta, W, Cr, Ti, or their nitrides), which would impair its adhesion to the electroplated copper; and e) be smooth, facilitate high-density nucleation, and provide excellent adhesion to the electroplated copper. These requirements can be readily met by use of the above-described combination seed layer.
Conclusion
Fabricating copper interconnects using HAR openings can provide great benefits, including reduced line resistance, RC delay, signal loss, power dissipation, and heating and thermal stress. Combination seed layers offer an opportunity to independently optimize seed-layer thickness over the sidewalls and the field. A very thin ALD seed layer (Ru or Cu) would provide fully continuous sidewall and bottom coverage on the most demanding HAR features, and a relatively thick PVD Cu seed layer would provide adequate surface conduction. The throughput of the combined seed layers would be similar to a single PVD seed layer, since the ALD seed layer would be very thin.
In view of the wide use of double barrier layers (PVD-Ta/PVD-TaNX and, recently PVD-Ta/ALD-TaNX), it is remarkable that the seed layer has been neglected for so long. Equipment vendors’ assertions that a single PVD Cu seed layer is still adequate for present and future generations have been problematic. Single PVD seed layers play a critical role in poor device reliability (SIV and EM) and yields. Combination seed layers enable robust and consistent void-free filling of the most demanding HAR interconnects.
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Uri Cohen is the owner of UC Consulting, 4147 Dake Ave., Palo Alto, CA 94306; ph 650/494-0268; e-mail [email protected].