Issue



Evaluating topcoat options for immersion litho resists


07/01/2006







Three resist systems are commonly available for 193nm immersion lithography: resist with solvent-soluble topcoat, resist with an aqueous developer-soluble topcoat, and special 193i immersion resist needing no topcoat at all. This paper reviews the advantage and disadvantages of these systems, focusing on developer-soluble topcoat.

Chip manufacturers have widely accepted 193nm immersion photolithography as a viable solution for half-pitch nodes all the way down to 45nm and possibly beyond. As the name “immersion” implies, resist has to be exposed under a fluid-currently water. Conventional 193nm photoresists that are optimized for “dry” exposures are not suitable for immersion exposure since resist components show some solubility in water and thus leach out, thereby contaminating the water and deteriorating litho performance. The contaminated water can further degrade the front lens and wafer stage of the scanner. Water can also permeate into the resist film, causing resist swelling and changing its photochemical properties.

Topcoat process

An additional topcoat layer is an effective solution to block both the leaching of resist components into the water and the water permeation into the photoresist. The topcoat is spin-coated on the resist and is transparent at 193nm wavelength. There are two types of topcoats: those only soluble in some solvent and those that dissolve in resist developer (aqueous TMAH). The topcoat layer is removed after exposure and post-exposure bake (PEB) but before pattern development. A dedicated topcoat solvent must be used to remove the solvent-soluble type, and this introduces an additional processing step as well as a track module. Figure 1 diagrams the processes needed for each type, with Fig. 1a showing the solvent option.


Figure 1. Process flow comparison of resist stacks with an a) solvent-soluble topcoat, b) developer-soluble topcoat, and c) without a topcoat.
Click here to enlarge image

For developer-soluble topcoats, the topcoat removal step can be done in the develop module and integrated into the develop module recipe, as sketched in Fig. 1b. Most developer-soluble topcoats have a very high dissolution rate-over 100nm/sec. Practically, the development time doesn’t need to be adjusted to adopt this topcoat removing process, i.e., the develop module recipe stays the same. Most vendors currently appear to be focusing on developer-soluble topcoats. Of course, water-insensitive immersion resists would need neither an additional coating step nor a topcoat removal step. This case appears in Fig. 1c.

Selection of a developer-soluble topcoat

Leaching tests. Leaching tests measure the amount of resist components that can pass through the topcoat and leach into the water. So far, no standardized leaching test method or leaching specification is accepted by the whole community of material vendors, scanner vendors, and IC manufacturers.

We extracted leaching water samples using the water extraction and analysis (WEXA) apparatus and technique described by Hinsberg [1]. DI water was flowed over a resist and topcoat stack, forming a puddle on the surface. After a certain period of time (~1 min.) the water sample is extracted and analyzed. Leaching has been proven to be a quick process-it happens within 30 sec of water contact-and with 1 min. of water contact time, the concentration of leaching components in the water is saturated [2]. Photo-acid generator (PAG) components (C1-C12 sulfonates) are analyzed by using the liquid chromatography-mass spectroscopy (LC-MS) method. A strict leaching spec is used in our facility such that a total leaching level of sulfonates ≤5ppb is required for exposing an unlimited number of wafers.

Numerous developer-soluble topcoats were evaluated on typical 193nm “dry” resists. Almost all the topcoat samples that we tested can effectively work as barrier layers and reduce the leaching level of resist components to below 5ppb.

More directly related to lens degradation is the speed that resist components leach through the barrier: the dynamic leaching rate. Water flow under the exposure head continues during exposure and leaching components are flushed away. Thus, the dynamic leaching rate can better describe the concentration of resist components in the immersion water under the front lens. ASML proposes that a PAG leaching rate of <1.6×10-12 mol/cm2/sec is needed to protect its scanner [3], while Nikon suggests a PAG leaching spec of 5×10-12 mol/cm2/sec and an amine leaching spec of 2×10-12 mol/cm2/sec [4].

Optical requirements. In addition to preventing leaching, some topcoats can also serve as top anti-reflection coatings (TARC). To effectively reduce the reflection, the topcoat’s refractive index has to align with the reflective index of water and the resist, i.e.,

ntc = (nwater × nresist)1/2

The topcoat thickness also has to be optimized to ensure that reflections from interfaces destructively interfere. For light with an incident angle of zero, i.e., corresponding to the small NA situation, the topcoat thickness should be around λ/4ntc. Most topcoat samples are targeted near an ideal refractive index of about 1.56 and a thickness of 30.9nm. For light with a high incident angle or high NA, the calculation of optimal thickness is more complex; the thickness corresponding to the 1st reflective minimum increases with the incident angle.

Chemical requirements. When selecting a resist and topcoat combination, the topcoat solvent should not dissolve in the resist; otherwise, an intermixing layer may form. Most 193nm resists use PGMEA and PGME as their solvent, and topcoats have an alcohol-based solvent system. To prevent defect formation, special attention has to be paid to the solvent cleaning procedures.

Evaluation criteria

Process window comparison. Process window size is an important figure of merit for combinations of resist and topcoat. Figure 2a shows the process window obtained from a promising stack. A maximal DOF of ~1.1μm can be obtained for 90nm/90nm dense features with a binary intensity mask and annular illumination with σi/σo=0.55/0.85 at 0.75NA. A cross-section taken at best dose and focus is shown in Fig. 2b.


Figure 2. a) Process window for 90nm dense lines and space with a near-optimal topcoat; b) cross-section image taken at best dose and focus.
Click here to enlarge image

Further tests include an across-wafer CD uniformity assessment and a PEB delay test for 90nm 1:1 dense features. For the best-performing resist/topcoat stack, the average CD across the wafer is 96.0nm, and the 3σ of the CD is 4.5nm. Both the top and bottom CDs of the resist lines do not change with the PEB delay time, up to 15 min.

Resist loss caused by topcoat. We have observed that using some topcoats can cause resist loss. Figure 3a shows the measured contrast curves from 200nm resist with different topcoats (TC1, TC2, and TC3). With the dose near threshold, resist with TC3 loses the most and that with TC1, the least. Figure 3a also reveals a negligibly small thickness change after the removal of topcoat without exposure. This suggests that the topcoat-induced resist loss has to do with the photoreaction.


Figure 3. a) Contrast curves measured from stacks of the Resist A with different topcoats; b) average CD measured from 90nm/90nm resist stacks with different topcoats; c) X-sections. The resist pattern heights are 171, 162, and 152nm in the three images.
Click here to enlarge image

The resist and TC1, TC2, and TC3 stacks were exposed at the same dose and focus for 90nm/90nm dense patterns. The CD of the resist patterns was measured and plotted in Fig. 3b. With TC3, the average CD of the resist patterns is the smallest, which again suggested TC3 enhanced resist sensitivity. Cross-section images of resist patterns with different topcoats appear in Fig. 3c. About 50nm of resist loss is measured from the resist/TC3 stack; with TC1, loss is only ~30nm.

Process parameter optimization. The resist/topcoat stack has to go through three baking steps: post-apply bake (PAB) of resist; PAB of topcoat; and PEB. All require optimization of bake temperatures to get the best imaging performance. Figure 4a shows contrast curves of the best-performing stack measured at different bake temperatures. The strong influence of temperatures on contrast curves is observed, especially in the shoulder regime in Fig. 4a. In that region, the temperature combination of 105°C/80°C/110°C (resist PAB temperature /topcoat PAB temperature /PEB temperature) gives the smallest amount of resist loss. Fig. 4b shows the cross-section images of the resist pattern baked at temperatures of 105°C/80°C/110°C and at the original temperatures (110°C/90°C/115°C). In Fig.4b, the resist pattern processed with the original bake temperatures has additional resist loss of ~10nm compared to that of 105°C/80°C/110°C.


Figure 4. a) Contrast curves measured at different bake temperatures; b) cross-section images of resist patterns processed at bake temperatures of 105°C/80°C/110°C and plan of record (POR) temperatures (110°C/90°C/115°C).
Click here to enlarge image

The optimized PAB temperatures of both resist and topcoat are lower than that of the original conditions chosen. We believe that decreasing the PAB temperatures may change the PAG distribution in the resist. The original resist PAB temperature was optimized for the 193nm “dry” litho process with a single-layer resist on BARC. However, in the immersion process, the resist actually has to go through two bakes; unless the resist PAB temperature is decreased, the resist is actually over-baked by the topcoat PAB.

Defects introduced by topcoats

Defect reduction is a major task for 193nm immersion lithography. Based on their sources, the 193nm immersion defects can be categorized into defects introduced by the scanner, by materials, and by the process. Defects introduced by the material-BARC, resist, or topcoat-include small or large particles from the material itself and from the residual of the intermixing layer between resist and topcoat, micro-bridging on the resist pattern, and water marks caused by topcoat imperfections. Defects introduced by the process include wafer-edge particles: Resist or topcoat film at the edge of the wafer may peel off and generate particles, which may be moved around the wafer by the immersion head.

Different strategies have been proposed to reduce the defect counts for each defect source. Here we only discuss the defect reduction efforts on topcoats. The hydrophobicity of the topcoat surface and the dissolution rate of topcoat in standard TMAH developer are believed to be the two key parameters that are directly linked to the defect counts.

Hydrophobicity. In the immersion scanner, water is confined between the lens and wafer. The water meniscus moves with the exposure head, as sketched in Fig. 5a. The static contact angle is not sufficient to describe the situation. Dynamic contact angles have to be introduced, one for the advancing contact angle, labeled as θa, and one for the receding contact angle, labeled as θr in Fig. 5a. The dynamic contact angles are dependent on the height of the water gap, velocity of the wafer stage, and hydrophobicity of the topcoat surface.

It is believed that for smaller receding contact angles, water droplets may be left behind. If the receding contact angle is zero, a water film will be left-so called “film pulling.” Water left behind will form circular defects: water marks. To reduce or eliminate the water droplets, a large receding contact angle is needed, which implies increasing the hydrophobicity of the topcoat surface. However, the advancing contact angle also increases with the surface hydrophobicity.


Figure 5. a) Dynamic contact angles of water meniscus in exposure head; b) high advancing angle entraps bubbles; c) tilting wafer method to measure the dynamic contact angles and sliding angle.
Click here to enlarge image

High advancing contact angle means that the water meniscus, as sketched in Fig. 5b, easily entraps air bubbles. So, the dilemma is that with a hydrophobic topcoat, the water-mark defects get reduced but the bubble defects increase. The good news is that scanner vendors all have announced “bubble-free” designs of exposure heads [3, 4]. If the bubble entrapment can be solved by a new design, topcoat vendors can increase the topcoat hydrophobicity to reduce water-mark defects. The dynamic contact angles can be measured by using the tilting wafer method [5], as sketched in Fig. 5c.

Dissolution rate in developer. A high dissolution rate in developer is essential for the effective removal of developer-soluble topcoat and the reduction of defects introduced by the topcoat, especially the so-called “blob defect.” The blob defect, also known as the “satellite spot defect,” is typically composed of topcoat material re-deposited on the surface during the development and rinse steps. They are mostly found in low pattern density areas, and have a diameter of 1-10°. It has been demonstrated that with the solvent-soluble topcoat, the immersion defect counts can be reduced to 0.1/cm2 [4].

Resist without topcoat

An effective resist without topcoat would be the preferred material for production. Its simplified resist process does not require separate coating and baking steps for the topcoat material and thus promises reduced cost of ownership and fewer sources for defects (see Fig. 1c). Conventional 193nm resists that have been optimized for “dry” performance do not appear suitable for immersion lithography without topcoats because of the observed high leaching rate. However, simultaneous requirements for minimized leaching behavior and superior overall litho performance have proven challenging for resist designers.

Several immersion capable (193i) resist samples have been evaluated using the same procedures described previously, with the 90nm 1:1 dense line and space target features. The maximal DOF of 1.0μm and maximal exposure latitude of 8% are obtained with one 193i resist without topcoat. Compared to the “dry” resist/develop-soluble topcoat stack described previously, the process window of the 193i resist without topcoat was about 15-20% smaller. Rinsing the resist film with DI water before exposure (so-called pre-rinse) was suggested as an alternative way to remove the major leaching components and it does work. The leaching level of the pre-rinsed wafers was reduced to about ~12% of that of the non-rinsed wafers [6].

Conclusion

While resist without a top protection coating may be the process most preferred for production, and although solvent-removable topcoats for “dry” resist have advantages that may outweigh their process complexities, “dry” resist with a developer-soluble topcoat appears to be capturing the mainstream. The developer-soluble topcoat process is relatively easy to implement in current manufacturing as a replacement for the “dry” litho process. With topcoats, resist designs so far have not needed to be changed; resolution, LER, profile, etc. are already optimized. To get the best process window, the topcoat and resist must be compatible, and the PAB temperatures of resist and topcoat as well as the PEB temperature have to be aligned to reduce resist loss. With the best resist and developer-soluble topcoat, a maximal DOF of ~1.1μm can be obtained for 90nm/90nm dense features with a binary intensity mask. The hydrophobicity and dissolution rate in developer are the two key parameters that affect defectivity behavior of the topcoat. Hydrophobicity in the topcoat helps to reduce water droplets or water-mark defects, while a high dissolution rate helps to reduce the blob defects.

Acknowledgments

The work was jointly done by AMD, ANT, IBM, Infineon, and Micron. The authors thank AZ Electronic Material, JSR, Rohm and Haas, ShinEtsu, Sumitomo, and TOK for supplying resist and topcoat samples; the operational infrastructure at Albany Nanotech; and the technical teams and their managers of AMD/IBM/Infineon/Micron.

References

1. W. Hinsberg, G. Wallraff, et al., Proc. SPIE, 5376, 21, 2004.

2. W. Conley, R.J. LeSuer, et al., Proc. SPIE, 5753, 64-76, 2005.

3. B. Streefkerk, C. Wagner, et al., Pres. at the Sematech 2nd 193nm Immersion Symp., Brugge, Belgium, Sept. 14, 2005.

4. K. Nakano, S. Nagaoka, S. Owa, Pres. at the Sematech 2nd 193nm Immersion Symp., Brugge, Belgium, Sept. 14, 2005.

5. C. Van Peski, A. Grenville, et al., Pres. at the Sematech 2nd Immersion Symp., Brugge, Belgium, Sept. 14, 2005.

6. R.R. Dammel, G. Pawlowski, et al., Proc. SPIE, 5753, 95-101, 2005.

Yayi Wei is a staff engineer in advanced lithography development at Infineon Technologies, NanoFab 300-South, 255 Fuller Rd., Albany, NY 12203; ph 518/956-7057, e-mail [email protected].

Karen Petrillo is an advisory engineer in the lithography technology development department at Albany Nanotech.

Peter A. Benson works for Micron Technology Inc. as a photolithography development engineer in the R&D fabrication facility.