IBM constructs IC along single-walled CNT
06/01/2006
IBM researchers have fabricated a CMOS-type ring oscillator circuit entirely on one 18µm-long, single-walled carbon nanotube (SWCNT) (Figs. 1 and 2) using standard semiconductor processes [1], and taking advantage of the CNT’s long, thin structure.
To obtain both p- and n-type FETs on the same SWCNT, the polarities of the FETs were controlled by using metals with different work functions as the gates. Palladium (Pd) was selected for the metal gate for the p-FET and aluminum (Al) was chosen for the n-FET. Five such p/n-FET pairs were arranged side-by-side on one SWCNT to form the ring oscillator. The team reported circuit speeds nearly a million times faster than previous circuits that used multiple CNTs. The IBM group achieved a 52MHz output signal from the oscillator-still fairly slow compared to silicon-but DC measurements of the circuit suggest that it could be capable of reaching the THz range.
A key results enabler was selecting Pd for the contacts for both the p- and n-FETs. Joerg Appenzeller noted that previous work by one researcher, Zhihong Chen, showed that two ingredients are important for driving current through FETs based on CNTs: the contact material chosen and its diameter.
Summarizing Chen’s work, Appenzeller explained that Pd is a large work-function material that offers a good lineup with the valence band of the CNT; choosing a lower work function material would give a better lineup with the conduction band of the CNT. “A Pd contact is good for hole-injection into the valence band, and a small work function metal, like Al, would be good for electron injection into the conduction band,” said Appenzeller. “The larger the diameter of the CNT, the smaller the energy gap between the conduction and valence bands…and the smaller this gap, the easier it is to inject both electrons and holes. If we choose a diameter that corresponds to a rather small energy gap, we have a very good carrier injection of holes and electrons and a correspondingly high current.”
 Figure 2. A CMOS-type five-stage CNT circuit layout. |
Even though Pd is a good choice for p-FETs but not ideal for n-FETs, by choosing Pd for both p- and n-FETs, the researchers were able to keep the project as simple as possible. “We already had five e-beam layers…we didn’t want to make a sixth layer for a second metal, so we compromised and used only Pd for both p-FETs and n-FETs,” explained Appenzeller. The top gate contact for the n-FET was Al, and the p-FET top gate contact was Pd.
The IBM team believes that new nanofabrication processes will eventually unlock superior performance of CNTs. “From the DC performance, one can extrapolate what can happen in a circuit operating at a very high frequency,” explained Appenzeller. “Because CNTs have a very high carrier velocity and almost no scattering in the channel, that translates to high currents.”
To unlock the THz potential, Chen said researchers can play with the diameter of the CNTs and the circuit layout, such as by optimizing the substrate contact dimensions, the channel length, the type of metal contacts, or the gate dielectric.
The IBM team collaborated with two universities for this project: the U. of Florida provided the CNTs, and the U. of Columbia produced the ALD gate dielectric film (an aluminum oxide that isolates the gate metal from the CNT channel). Appenzeller noted that at the time of the original work, IBM did not have these capabilities, but it is now able to grow CNTs and also form the gate dielectric.
Adding more CNTs wouldresult in more complex circuits, but Appenzeller noted that researchers have to first figure out how to build such circuits and align all of the CNTs together. For example, crosstalk (generated by fringing field effects between two CNTs close to each other in parallel) would have to be accounted for-and nobody knows how to even make arrays of CNTs in parallel, let alone know how close together two CNTs can be before there is a crosstalk problem. These challenges and others remain, but he said that IBM is ramping up efforts to explore them.
One challenge that needs to be addressed as researchers continue to pursue THz frequencies with CNT circuits is a limitation on measuring the small currents in them. There is an impedance mismatch between the output of the ring oscillator and the input of the spectrum analyzer that is used to make the measurements-the input impedance of the spectrum analyzer is 50Ω, while the CNT ring oscillator’s output impedance is on the order of megaohms. “So we see very small signals (on the order of microvolts and microamp currents),” said Chen. “We will need to solve this mismatching problem if we want to eventually integrate CNTs into silicon devices or circuits.” Chen believes CNTs could probably be used in parallel, thereby boosting the current into the milliamp range. “Then we can match our CNT circuits to the silicon circuits.”
Appenzeller was not able to give a timeline for actually getting CNT circuits to operate in the THz range. However, he noted that it is well-known how to make these ring oscillator circuits faster using conventional CMOS techniques and suggested that bringing these circuits within the performance range of silicon is feasible within a couple of years. -D.V.
1. Z. Chen, J. Appenzeller, Y-M. Lin, J. Sippel-Oakley, A. Rinzler, et al., “An Integrated Logic Circuit Assembled on a Single Carbon Nanotube,” Science, Vol. 311, March 24, 2006.
Future dielectrics for interconnects
The Materials Research Society (MRS) Spring Meeting in San Francisco drew thousands of technologists from around the world for a week of presentations and posters on the latest R&D and manufacturing results. Seven of the 34 parallel sessions fell into the general category of “microelectronic device processing and fabrication.” Many presentations, particularly those on low-k dielectrics, were attended by standing-room-only crowds.
IBM’s Advanced Organic Materials Group showed the results of some pure materials R&D: a new spin-on oxycarbosilane dielectric (k=2.3) with exceptional mechanical properties. Among the potential candidates to serve as low-k insulators for copper backend-of-line (BEOL) interconnects, organosilicates (such as SiOC) can be spun-on or deposited by chemical-vapor deposition (CVD). Ultralow-k (ULK) nanoporous films can be obtained using a sacrificial porogen approach. The introduction of porosity into organosilicate thin films degrades the mechanical properties, with limited improvement through control of porous morphologies and post-porosity treatment using UV or e-beam exposure. IBM reported that the templated sol-gel polymerization of bridged oxycarbosilane monomer precursors improved the mechanical properties without using post-porosity treatments. For a given dielectric constant, the Young’s modulus of these oxycarbosilane films are 4×-5× higher than as-deposited organosilicates, and at least 2× higher than UV-treated organosilicate materials.
Researchers from the Crolles2Alliance presented results on the use of plasmas for pore sealing of damascene-patterned porous ULK materials. Various plasma conditions were evaluated for both single- and dual-damascene structures. For dual-damascene, trench-first hard mask integration without resist plugs, NH3 provided the lowest capacitance and RC product when used after dual-damascene etch. Pore-sealing with NH3 can be done after cleaning the etch polymers. However, Philips Research in Leuven, Belgium, showed that some plasma conditions can induce substantial damage to ULK materials, so care must be taken with overall process integration.
Although CVD and spin-on processes can be used to form porous SiOC films, either way the film skeleton is mainly made of Si-O-Si bonds with methyl groups linked to silicon. The films’ elastic properties, determined by using nano-indentation, can be correlated to the Si-O-Si concentration in the porous film. This means that, for a given density, the material cross-linking mainly governs the film elastic properties independently of the deposition technique used.
Kelin Kuhn of Intel in Hillsboro, OR, commented on porous low-k dielectrics in answering a question regarding fully silicided (FUSI) NiSi metal gates and uniaxial strained silicon channels. Intel showed that metal gates eliminated poly-Si gate depletion, and improved inversion charge density by 20% with corresponding 20% gains in IDSAT and IDLIN, and were fully compatible with uniaxial strained silicon. Regarding overall capacitance in CMOS transistors, Kuhn said, “You want to use the lowest-k spacer possible. If I could use porous low-k, I would…but when we tried porous spacers, we found tungsten diffused into the pores.”
Romano Hoofman, representing Philips Research and the Crolles2Alliance, provided an excellent overview of the possibilities of air-gap integration as a viable alternative to porogen integration. Different air-gap integration approaches can be used to fabricate multilevel interconnects. All approaches can be classified as follows: partial or complete material-removal between metal lines, followed by nonconformal CVD deposition, or damascene integration of metal lines in a sacrificial material, which can be selectively removed through a dielectric cap (see figure).
 Schematic cross-sections showing possible air-gap variations for on-chip interconnects. |
Interconnects containing air-gaps do not have more reliability problems than interconnects with porous low-k dielectrics-therefore, air gaps might be considered as a viable option for the 32nm node and beyond. “Simulations have shown that we get sufficient benefits from the use of air-gaps in two or three metal levels,” Hoofman stated, adding that “we do not suggest using air-gaps at all metal levels.” Also, since design and manufacturing trade-offs will be managed in nanometer node production, design constraints such as forbidden gaps may greatly simplify air-gap integration. -E.K.
Mapping the road to NIL
Researchers at Georgia Tech and Sandia National Laboratories have concluded a three-year study that identifies key parameters determining the outcome of the nanoimprint lithography (NIL) process, in essence developing a “roadmap” of the technology.
Using results from experimental work and a codeveloped simulation program, a team led by Georgia Tech assistant professor William King examined every variable involved in the nanoimprinting process, including shear deformation of the polymer, elastic stress release, capillary flow, and viscous flow during the filling of imprinting tool cavities, and recorded the outcome of each incremental change through the design space. Specific work focused on, for example, how large differences in cavity sizes on the imprinting tool lead to nonuniform filling and nonlocal polymer flow, as well as recommending how such issues could be minimized.
Ultimately, the research revealed parameters that determine the process outcome, such as key geometric factors that can be used to predict the polymer deformation mechanism (see figure). The team also developed a nondimensional measure, the “nanoimprint capillary number,” to help predict the mechanism that governs polymer flow details. Reducing the complex set of variables to key parameters allowed the team to account for varying process outcomes reported by scientists in other papers, King noted.
 Nanoimprint lithography cavity and deforming polymer, showing simulation boundary conditions, geometry variables and polymer peak deformation location measurement. |
The results apply to any polymeric material that follows standard viscous flow rules and produces >50nm feature sizes. The next step in the research is to modify the simulation software to account for physics changes at the nanoscale.
“This work provides a rational link between what engineers want to make using nanoimprint lithography and the path for creating [the structures],” stated King. “We have developed manufacturing design rules that will give future users of this technology a predictive tool kit so they’ll know what to expect over a broad range of parameters.”
Results of the work, which was supported by the National Science Foundation and US Department of Energy, were published in the Journal of Vacuum Science Technology B and the Journal of Micromechanics and Microengineering. -J.J.M.
Samsung tips 3D memory package
Samsung Electronics Co. Ltd. says it has developed a wafer-level processed stack package (WSP) of high-density memory chips that is 15% smaller and 30% thinner than an equivalent wire-bonded multichip package, using through-silicon via interconnects. The device incorporates eight 2Gbit NAND flash chips, each 50µm high, vertically stacked to a height of 0.56mm.
 Single wafer before back-grinding. |
Using WSP, micron-sized holes are drilled through the silicon vias instead of using conventional dry etching methods, eliminating photolithography processes required for mask-layer patterning and shortening the dry-etching process needed to penetrate through a multilayer structure. The WSP process also reduces the length of the interconnects, resulting in a 30% boost from lower electrical resistance, the company notes.
 Eight stacked chips (WSP). |
Samsung plans to apply the WSP packaging technique initially for its NAND-based memory cards in early 2007, and later for more high-performance system-in-package (SiP) and high-capacity DRAM stacks. -J.J.M.
Integrated MBE process for IR detector
Infrared detectors for applications such as missile seeking, targeting, navigation, and night-vision goggles are costly and involve complex processing, often on 2-in. wafers. A newly integrated molecular beam epitaxy (MBE) process enables production of high-resolution, third-generation IR mid-wave mercury cadmium telluride (MCT) detectors on 4-in. wafers, according to Sofradir, Grenoble, France. New Jupiter IR detectors pack more than one million pixels onto a 1280 × 1024 pixel MCT device at 15µm pitch, operating in the 3-5µm waveband. A linear 1W microcooler enables operation at 90K (-183°C).
The integrated MBE process was developed with LETI (Laboratoire d’Electronique de Technologie de l’Information) through a joint laboratory called DEFIR (Design of Excellence for the Future of IR). This lab is the only one in Europe to industrialize the process, according to Sofradir. Moving from 2-in. to 4-in. wafers can achieve a 4× capacity increase for some types of detectors. An expanded facility for production with the 4-in. wafer process is planned for mid-2007. -B.H.
New squeeze for advanced photoresists
A packaging system for direct pressure dispensing of photoresist chemicals was recently announced by ATMI Packaging. Developed in conjunction with TEL, chemical suppliers, and end users, the new system, called PDMPak, was designed to minimize microbubbles and misconnects.
Microbubble formation is a problem that has been around for a long time, in both i-line and DUV resists, according to Stephen Strausser, VP of marketing at ATMI. Addressing the problem required a chemical delivery solution that continuously pressurizes the chemicals “in the bag” without entraining gas within the chemicals. “A traditional bottle would have the inherent microbubbling effect because the gas used to pressurize the liquid in the bottle is constantly and directly pressurizing the liquid
esist...so you’re entraining the gas into the chemical at that point,” explained Strausser. ATMI’s technology incorporates a liner, acting as a barrier between the elbow or plastic bottle and the chemistry in the bag, “so the gas is on the outside squeezing the liner, which is then squeezing the resist out of the bottle, and keeping it fed to the line,” he said.
By eliminating headspace, the liner also prevents air from becoming entrained when the liquid is finally delivered in the bottle to the site. “If you had only a bottle and no liner, you’d be forcing the gas into the liquid as it is being pushed out,” noted Strausser. “As the resist leaves, air would be left as a replacement, which further gets entrained in the remaining resist.”
According to Rob Crowell, product marketing manager for Clean Track, at TEL, the supplier of track tools initiated a development program to focus on the entire chemical delivery system, to address defect and dispense quality requirements for advanced nodes. The design changes, including those that decrease chemical waste, were incorporated into the Lithius platform, targeting the 45nm node and beyond. ATMI expects to release the new version of the PDMPak in 3Q06. -D.V.
Tech Briefs
Spin is in for TFT fabrication
Aiming to find a low-cost, high-throughput process for fabricating high-performance thin-film transistors (TFT), researchers at Seiko Epson and JSR Corp. have created a high-quality silicon film formed with a spin-coat method and inkjet patterning processes, with performance comparable to films developed through conventional CVD methods.
Typical manufacturing processes for silicon film, used with low-temperature polysilicon TFTs, are formed in vacuum devices using photolithography equipment to transfer the pattern. Research has been conducted in recent years to create organic semiconductors formed from liquids, eliminating the need for vacuum devices and enabling printing technologies such as inkjet to create the pattern.
The new material, developed by Epson and JSR, is a high-order silane compound of hydrogen and silicon (cyclopentasilane, Si5H10) dissolved in an organic solvent, spin-coated on a substrate and baked at 540°C in an inert atmosphere, forming a 50nm-thick amorphous silicon film. Irradiation by a 308nm XeCl excimer laser turns the film into a polycrystalline Si, with measured electron mobility of 74-108 cm2/Vsec, approximately equivalent to that achieved by the CVD method. A TFT prototype using a silicon film pattern created by inkjet method instead of spin-coating showed electron mobility of 6.5 cm2/Vsec, lower than that achieved with spin coating.
More research is ongoing to control the oxygen levels in the organic dilutent (toluene in this case), and to understand the “wettability” of the film during inkjet application, in order to control ink droplet sizing to create layers thin enough for laser crystallization.
The research was commissioned by Japan’s New Energy and Industrial Tech-nology Development Organization (NEDO).
Early success with 22nm memory switch
Nantero Inc. says it has successfully demonstrated scalability of its nonvolatile random access memory (NRAM) technology, with fabrication and testing of a 22nm NRAM memory switch.
The NRAM switches are fabricated using a proprietary fabric webbing made of masses of tangled carbon nanotubes, and a ribbon of the fabric as a mechanical switch between electrodes-much like the mechanical relays in the first computers. An array pattern of ribbons of nanotube webbing can thus be formed across the chip, suspended over interconnect trenches. Sending a charge through the ribbon makes it sag down into the trenches to contact the electrodes; when the power is removed, Van der Waals Forces maintain the ribbon in its flexed state.
The company indicates that the 22nm device was created in its Woburn, MA, lab using electron-beam lithography (no production-scale 22nm lithography yet exists), and was tested by writing and reading data using 3 nsec cycle times. Also, the company says its NRAM process validation continues to involve LSI Logic, with whom Nantero presented initial results last summer of integration with 0.18µm logic devices, with the goal of replacing embedded SRAM at 90nm and 65nm. ASML’s special applications group helped validate Nantero’s process with fab equipment.
Nantero currently is in development for other conventional CMOS process nodes in production, using existing tools and processes. The company believes the process will scale down to future generations, even below the 5nm technology node.