Semicon West 2006
06/01/2006
The 36th annual SEMICON West conference and exhibition will be held in San Francisco again this year with new special areas devoted to solving challenging problems. The conference program will run from Monday, July 10-Thursday, July 13, while the exhibition will run from July 11-July 13. The wafer processing area of the exhibition will be located in the Moscone Center’s North, South, and Gateway Halls, and the final manufacturing area will be located in the West Hall, Levels 1-3.
This year, the program will consist of business and technical programs; Technology Innovation Showcase presentations; IEMT professional development courses (PDC); SPIE, IEEE, and PTI short courses; standards meetings; and standards technical education programs. In addition, special areas called TechXPOTs will feature live technical sessions exploring trends, challenges, and opportunities in micro- and nanoelectronics design, manufacturing, assembly, packaging, and test.
Below is a condensed list of programs and events, which all take place at the San Francisco Marriott unless otherwise specified. To check for availability of these courses, or to register on-line, visit the Semi web site at http://www.semi.org/semiconwest. For more information, call SEMI at 408/943-6901. Registration for programs/events by June 9 includes free admission to the exposition. On-site exposition registration is $75.
Technical Programs and Events
Monday, July 10-Tuesday, July 11
• Semiconductor Account Selling, SEMI Headquarters
• STG Presents: Equipment Reliability and Productivity Assessment Standards
Monday July 10-Wednesday, July 12
• Semiconductor Processing Technology (SPT)
Monday, July 10
• IEEE/CPMT PDC: Advanced Packaging Technology Solutions for Today’s Leading-edge Microelectronics
• IEEE/CPMT PDC: 3D Packaging Developments and Trends
• Introduction to Advanced Process Control for Semiconductor Manufacturing
• STG Presents: SEMI Standards Sort Map
• SEMI Market Symposium
• IEEE/CPMT PDC: Introduction to Flip Chip Technology, A User’s Guide
• IEEE/CPMT PDC: Design, Materials, Process, and Reliability of Lead-free Packaging and Assembly
• IEEE/CPMT PDC: Introduction to Nanotechnology: Tools, Processes, and Applications
• Polarization for Lithographers
• STEP: Developments in ESD Standards for Semiconductor Equipment
• SEMICON West President’s Reception
Tuesday, July 11
• STEP: The New SEMI E33 Specification for Semiconductor Manufacturing Facility and Equipment Electromagnetic Compatibilty
• The Fundamental Limits of Optical Lithography
• Developing and Implementing Intellectual Property Strategies in the Semiconductor Industry
• Global Care Forum: Putting Your EHS Commitment into Practice
• Opening Ceremony Keynote Address: Laurent Bosson, STMicroelectronics, Moscone Center, West Hall
• Keynote Address: Jim Healy, LogicVision, Steve Anderson, Surfect Technologies, Moscone Center, West Hall
• Pushing the Limits: Optical Enhancement, Polarization, and Immersion Lithography
Wednesday, July 12
• STEP: Developments and the Future of Wafer-edge Profile
• STEP: Measuring Your Equipment Efficiency and Why It Makes Sense
• Introduction to Modern Chip Design Methodologies
• Keynote Address: Willem Roelandts, Xilinx, Moscone Center, West Hall
• Keynote Address: Steve Appleton, Micron, Moscone Center, West Hall
• STEP: What’s New in SEMI S2 for 2006
• EHS Interest Group Meeting: Does 1st July 2006 RoHS Enforcement Signal a Paradigm Shift?
Thursday, July 13
• STEP: The Present and Future of RFID in the Semiconductor Industry
• Understanding & Using Cost of Ownership
• Investment Conference: “The Bulls and Bears” Midyear and Beyond, Moscone Center, West Hall
Exhibition Hours
Tuesday, July 11, 10:00-6:00
Wednesday, July 12, 10:00-6:00
Thursday, July 13, 10:00-4:00