Late-porogen removal integration for ultra-low-keff IMDs
06/01/2006
The value keff has become a valuable metric for evaluating the quality of the final integrated intermetal dielectric (IMD) film stack. Achieving the ITRS projection of 2.5 keff for interconnect dielectric by the end of the decade may require the integration of highly porous ultra-low-k films. Moreover, integration must occur with minimal process-induced dielectric damage. To this end, a Sematech dual-damascene integration approach has been developed that entails stopless integration and a post-CMP, or “late,” porogen-removal process. Low-damage CMP, etch, ash, and dielectric-cure processes were integrated to demonstrate an intraline keff of 2.5. In addition, preliminary results show that a new spin-on dielectric with relatively higher-temperature stability can be integrated with a PECVD hardmask for enhanced reliability, though with slightly higher integrated keff.
The maximum speed at which an electromagnetic pulse can propagate through a metal line surrounded by a dielectric is proportional to the resistance of the metal (R) times the capacitance of the dielectric (C), a factor limit which is commonly known as the RC time constant. The capacitance of the dielectric is proportional to the permittivity, or dielectric constant (k), of the material, and multiple materials in a complex dielectric structure combine their k values as weighted averages of their volume incorporation within the structure. For example, air has k=1, so adding ~50% pores of air to a dielectric with k=3 results in a final porous dielectric with bulk k=2. However, complete IC interconnect processing typically requires at least one additional dielectric layer to function as a hardmask, and thus the relatively higher k value of this layer creates a higher effective k (keff) for the overall structure.
The 2005 ITRS projects that keff will be lowered to 2.5 at the end of this decade, using bulk dielectric films with k≤2.2 [1]. One of the key challenges to achieving this low-keff goal is minimizing process-induced dielectric damage that can be caused by etch, ash, chemical mechanical planarization (CMP), and metallization processes. Sematech has demonstrated an intraline keff of 2.5 for a copper and ultra-low-k (ULK) dual-damascene integration approach using a post-CMP Solid First ILD porogen-removal process.
The late-porogen removal technology uses a methylsilsesquioxane (MSQ)-based dielectric matrix containing an acrylic polymer-based porogen that is thermally stable up to 275°C [2]. The matrix-porogen system can thus be processed as a dense material through CMP. A post-CMP furnace or UV-assisted thermal cure creates porosity by removing the porogen while further setting the matrix. This approach can minimize dielectric damage from other processing steps (e.g., etch, ash, CMP), and also prevent atomic layer deposition (ALD) precursor penetration without the need for additional higher-k pore-sealing layers [3, 4]. This integration used Zirkon LK2000v7 (k≈2.0) and VL2100v1 (k≈2.1) ILD as the bulk dielectric and hardmask, respectively. The hardmask was selected for its ash resistance and CMP selectivity.
Materials and processes
Wafers were processed on 300mm tools using reticles containing 90-nm node features, for a full via-first trench-last (FVFTL) integration. Etching was done using a capacitively coupled plasma-etch tool, and resist stripping was done using an inductively coupled plasma (ICP) and RF-source ash tool. Barrier deposition included an in situ argon pre-sputter etch (PSE) in order to clean the via bottom. CMP was performed on a conventional rotary hardware system using conventional commercially available slurries.
No delamination or cracking of the nonporous dielectric was seen during the CMP process. Post-CMP curing to remove the porogen and improve the film mechanical properties was done using either a 450°C furnace cure or a UV-assisted thermal cure at 400°C. Figure 1 shows a schematic cross-section of the integrated film stack using a combination of spin-on dielectric ILD films and a CVD silicon-carbon-nitride (SiCN) dielectric barrier. Porogen removal occurs during the curing step and additionally during the deposition of passivation layers.
Keff extraction methodology
The second-level metal (M2) keff was predicted and extracted using Raphael 2D capacitance modeling software. The complete dielectric structure contained the interlevel dielectric (via layer), intrametal dielectric (M2 layer), and SiCN dielectric barrier [5]. Extraction of keff was based on coupling the specific die capacitance measurements with critical dimensional values averaged from a minimum of three measurements using SEM or TEM cross-sectional analyses. Because a commercialized interconnect would have additional low-k layers above M2, the influence of the higher k of the corresponding passivation films was accounted for, and keff was further modeled assuming that a low-k dielectric would be used for the third-level metal (M3).
The metric of Δkeff (the difference between extracted and predicted keff) was used for analysis of dielectric damage as a function of dielectric spacing. For the ideal case of no process-induced dielectric damage, Δkeff would be zero and constant for varying dielectric spacing. However, with sidewall damage present, it is expected that Δkeff will increase with smaller dielectric spacing since the sidewall damage region becomes a relatively greater portion of the overall intrametal dielectric [5, 6].
Reducing dielectric damage
Using the keff extraction methodology, Figure 2 shows the development progress in reducing the integrated damage from Δkeff of 0.7-0.8 to about 0.1. Initial improvements lowered Δkeff to 0.6 by transitioning from a furnace to UV cure (this eliminated residual porogen that otherwise could elevate the post-cure bulk k value) as well as by changing from nonselective to selective Cu CMP slurry and removing the metallization Ar+ PSE [7]. Changing the etch chemistry to a less-polymerizing approach, using CF4/Ar/O2 instead of C4F8/Ar/N2 [8] provides several advantages. The less-polymerizing etch improved the trench profile. The better vertical profile also reduced the sputtering of the trench sidewall during the metallization, which likely contributed to further reduction in the Δkeff to 0.5, even with inclusion of the Ar+ PSE process.
 Figure 2. Δk eff improvement with integration development cycles and critical process changes. |
While using the C4F8-based etch chemistry, we have observed that the PSE process removed dielectric material from the trench feature top, sidewall, and bottom, whereas the CF4-based chemistry resulted in minimal sidewall material removed. Finally, Δkeff was further reduced to 0.2 using a combination of reduced etch and ash times to achieve the targeted trench depth, while clearing the resist during the ash using a 30% over-ash (ash time past endpoint detection).
After obtaining keff values within 0.2 of the predicted keff using SEM images for feature size measurements, more accurate TEM-based measurements were performed. The TEM-based keff measurements were consistent with the SEM-based measurements (Table 1), showing dielectric damage was significantly reduced, while more accurately indicating the Δkeff was 0.1 at minimum spacing. This minimal damage was supported by TEM-EELS results showing that carbon depletion at the dielectric/Ta barrier interface was <5nm for the ICP N2/H2 ash used throughout this study.
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The passivated M2 structure had a predicted keff of 2.75 with the assumption of zero-damage and the inclusion of higher-k passivation layers. Accounting for the influence of an M3 level above M2, and coupled with targeting a 20nm SiCN dielectric barrier, the predicted keff is reduced to 2.40. Table 2 summarizes the predicted and extracted keff results for 300nm pitch structures, showing that a keff of 2.51 was demonstrated for the case of M2 in a hypothetical three-level metal (3LM) interconnect. Further experiments would be needed to verify the 3LM extrapolation and assess the potential influence of that additional processing on the keff of lower interconnect levels.
There were some reliability issues identified with the VL2100v1 low-k hardmask that would require material improvement to meet manufacturability needs [4]. The reliability issues were addressed by the development of a new polymeric porogen material, LK2000v8+. This dielectric material has improved thermal stability (>300°C) and as such can be integrated using a sacrificial PECVD SiO2 hard mask to replace VL2100v1. The CMP removal rate for this SiO2 hard mask is similar to that for the main LK2000v8+ dielectric, which allows for easier process integration. Preliminary results for etch and ash feature smoothness (Fig. 3) suggest the feasibility of this revised integration approach.
Conclusion
This work has shown that the late-porogen removal approach is one potential solution to integrating highly porous ultra-low-k films with minimal damage while also preventing ALD precursor penetration. These will be critical properties for any advanced dielectric solution that can enable 2.5 keff. Challenges that call for further development include identifying viable lithography rework processes (simplified with incorporation of a sacrificial hardmask), understanding shrinkage-induced stress, and controlling copper line topography during UV-assisted thermal cure.
Acknowledgments
The authors would like to thank the Sematech ATDF for wafer processing and analytical support, numerous Sematech and Rohm and Haas colleagues who contributed to this project, and Axcelis Technologies for providing UV curing. Zirkon and Solid First are trademarks of Rohm and Haas Electronics Materials LLC. Sematech, ATDF, and Advanced Technology Development Facility are service marks of Sematech Inc. Raphael is a trademark of Synopsys.
References
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4. E. Engbrecht, et al., in Proceedings of the 2005 Advanced Metallization Conference, Colorado Springs, CO, September, 2005, in press.
5. B. Kastenmeier, K. Pfeifer, A. Knorr, Semiconductor International, 27(8), pp. 87-92, 2004.
6. F. Iacopi, M. Stucchi, O. Richard, K. Maex, Electrochemical and Solid-State Letters, 7(4), pp.G79-82 (2004).
7. S. Satyanarayana, B. White, R. McGowan, M. Gallagher, American Vacuum Society 6th International Conference on Microelectronics and Interfaces, 2005 (submitted to Journal of Vac. Sci. and Tech. B).
8. B. White, et al., Proceedings of the 2005 Materials for Advanced Metallization Conference, Dresden, Germany, March 2005, in Microelectronic Engineering 82, pp. 348-355, 2005.
Klaus Pfeifer received his masters in physics from the U. of Hamburg’s Institute for Solid State Physics. He is program manager for copper low-k module integration within Sematech’s Interconnect Division. He joined Sematech as an employee in 2003 after formerly serving the consortium as a Philips Semiconductors assignee. Sematech, 2706 Montopolis Drive, Austin, TX 78741-6499; ph 512/356-7061, [email protected].
Ward Engbrecht received his PhD in chemical engineering from The University of Texas at Austin. He was on assignment at Sematech from Texas Instruments, working on advanced interconnect copper/ultra low-k integration. He is currently in Dallas working on TI’s BEOL integration.
Michael Gallagher received his Ph.D. in inorganic chemistry from the Massachusetts Institute of Technology. He is R&D manager for advanced products at Rohm and Haas Electronic Materials LLC, where he is responsible for development of dielectric, topcoat, hardmask, underlayer, and remover materials.