Optimizing process window robustness with reconfigurable OPC
06/01/2006
In this work, a reconfigurable optical proximity correction (OPC) approach is taken to enhance process window robustness for sub-100nm designs. First, a physics-based method for lithography process window verification is used to provide better accuracy at off-focus and off-exposure conditions and to reduce calibration efforts, as compared to traditional empirical approaches. After multiple defocus and exposure conditions are simulated, reconfigurable OPC is used to fix only defective areas and to replace them with optimized corrections, thereby avoiding the possibility of generating new errors when fixing problematic patterns. This combined approach provides an optimal lithography solution that is robust across the process window, and a mask design inspection and optimization method that improves yield and shortens cycle time to first wafers.
OPCs applied to design layouts are targeted for the nominal process condition FoEo that maintains manufacturing throughput and yield. For designs at ≥130nm, this is usually sufficient to provide the needed resolution enhancement technology (RET) corrections for high-yield manufacturing. However, for sub-100nm designs, lack of feature fidelity across the process window becomes a significant contributor to yield loss. It becomes critical to simulate across the lithography process window to predict feature behavior over a wide range of focus and exposure (FE) conditions. KLA-Tencor’s DesignScan tool simulates the performance of a design across the process window and detects any defects, which are then flagged for repair.
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In the conventional OPC flow, correction of defects entails changing the OPC recipe and redecorating the entire layout. Aprio’s Halo-OPC incremental and reconfigurable OPC technology allows one to compute more aggressive OPC corrections at the error locations. This reconfigured OPC replaces the original corrections only at the error locations, allowing prior OPC results to be re-used. The halo, or boundary areas, associated with the stitching of the modified OPC are simulated and verified and the results are converged back into the layout. This approach allows the designer to start with a nominal OPC design, then apply reconfigurable OPC technology, eliminate printability errors in the process window, and expand the process window, resulting in more robust design performance across the process window.
In this work, the in-line inspection results are used to drive process window enhancements. Reconfigurable OPC is utilized for the design optimization, which simulates the defective areas only, and replaces them with optimized corrections that are robust across the process window.
Incremental reconfiguration
In the conventional design-to-manufacturing flow, once a design is complete and is design-rule checked (DRC) “clean,” it undergoes RET correction. The application of OPC and other RET techniques change the physical design, causing it to no longer equal the drawn layout [1]. For deep submicron lithography at ≤130nm, there are places in the FE process window where the physical design breaks down due to a weak pattern that may need additional OPC corrections that fall outside of the OPC recipe used. In the conventional OPC flow, if systematic yield-limiting features are identified, it necessitates changing the OPC recipe and rerunning OPC on the entire layout. However, by doing this on the entire layout, there is a likelihood of generating new errors while fixing the problematic patterns.
Currently, design teams perform tasks hierarchically, incrementally, and concurrently with design re-use. However, conventional OPC is applied sequentially and in batch operations to the full chip. With the conventional methodology, it is impossible to take an already OPC-corrected layout in GDSII or other data format and reconfigure only part of the layout without re-running OPC on the full chip. Using the technique outlined below, OPC correction is performed on a specified portion of an OPC-corrected layout. Other areas that do not require reconfiguration will be left untouched, thus preventing the possibility of generating new errors. Since this technique performs reconfiguration incrementally rather than on the full chip, it runs considerably faster than conventional OPC methods [2]. Reconvergence of the OPC into the layout is the process where the effects of the changed OPC on its neighboring geometries are considered. By simulating the effects in a halo region around the changed OPC that includes neighboring geometries, precise boundary matching is achieved and the OPC is seamlessly integrated or “stitched” back into the layout.
Experiments and results
In this section, we present the results of the verification engine tool and the OPC tool. The Halo-OPC tool is used for both creating the model-based full-chip OPC layout and reconfiguring the OPC where it fails within the process window. DesignScan takes the OPC GDSII output and simulates the layout across nine conditions in the focus-exposure matrix, defines the process window, and tags defects that occur within the process window. The defects are binned into the following categories: CD errors, line-end shortening, exclusion errors, bridges, breaks, and extra and missing printed features [3].
The experimental layout that was used is 8×8mm in wafer dimensions and is hierarchical. The poly layer nominally has half-pitch of 100nm with poly lines as small as 80nm. The lithography model parameters are summarized in Table 1. These parameters are used in the model that Halo-OPC uses to generate the model-based OPC layout and the simulation results in the verification engine in DesignScan.
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Simulation and verification of initial OPC layout. After model-based OPC is applied to the poly layer with the input litho process parameters, initial inline inspections of the OPC layout were performed at FoEo = 0nm, 17mJ/cm2. The process window was opened to ±50nm and ±1mJ/cm2 in focus and exposure, respectively. No process window defects were found within this process window. Table 2 and Fig. 1 summarize the inspection results.
 Figure 1. Process Map for initial inline inspection showing zero defects, to accompany Table 2. |
Adding programmed defects to OPC layout. The initial inline inspections show a robust process window with center FoEo = 0 ±50nm, 17mJ/cm2 ±1mJ/cm2. To demonstrate the efficacy of repairing the process window defects, we have added programmed defects to the OPC layout that will fail at the corners of the process window and at points sufficiently interior. Reducing the linewidth to 50nm at the defect locations created these defects. The failure that we expect will be a narrowing of the linewidth, commonly called pinching or necking, leading to broken lines at the process window corners. Figure 2 shows the creation of a representative program defect from the drawn layout, OPC correction, and edge biasing to create the above failure. The programmed defects were limited to one block for inspection purposes since the blocks repeat across the entire layout.
Simulation and verification of OPC layout with programmed defects. Re-inspection of the layout with programmed defects was performed over the same process window as the initial inspections and was done over the entire layout. The programmed defects fail as expected at the process window corners. However, an unexpected result emerged in that the programmed defects failed throughout the entire FE matrix as catastrophic gaps. This is due to the aggressiveness of the negative edge-bias given to these defects. The aggressiveness of the negative edge-bias was deliberately chosen to test the reconfigurable OPC repair capability of the tool. There were 350 programmed defect failures found in the block that contained them and no process window defects were found on the remainder of the OPC layout. Table 3 and Fig. 3 summarize the inspection results. Figure 4 shows images of the same programmed defect shown in Fig. 2 across the nine conditions of the FE matrix.
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The defects are binned into categories to group together all identical defects. The binning model employed by the verification engine inserts and leverages lithographically significant hierarchy in the design [3]. Figure 5 shows the grouping of the binned defects.
 Figure 3. Defect Process map for inline inspection, to accompany Table 3. |
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OPC defects
Repairing OPC defects. Once the defects have been located, identified, and classified, they are tagged for repair, which is straightforward. Since the GDSII file is hierarchical, it contains the physical design, the associated OPC layer, and a layer that contains the tagging properties. Using the GDSII grid coordinates, the Halo-OPC tool analyzes the OPC layer at the defect location and reconfigures, or applies new OPC corrections at that location. This knowledge of the design intent embedded into the hierarchical structure of the GDSII file enables the localized OPC reconfiguration. Once the OPC reconfiguration at the repair location is complete, the new OPC is converged by the tool into the layout [4]. A single CPU repaired the 350 defects in a 30 sec run-time.
To achieve the OPC repair with the same accuracy and pattern fidelity across the process window, we used the same litho process parameters that were used to create the original OPC layout. The expected outcome of the reconfigured OPC is that it should be equivalent to the original OPC. To validate that the OPC repairs are successful requires re-inspection and simulation across the process window.
 Figure 5. The programmed defects are binned into 18 categories. The catastrophic gap failure of defect 3 is in group 2, where 36 occurrences were found. |
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Validating the repaired OPC defects. Re-inspection of the corrected layout was performed over the same process window as the initial inspections and was done over the entire layout-over the same nine FE conditions as the previous inspections. No defects were found within the process window FoEo = 0 ±50nm, 17mJ/cm2 ±1mJ/cm2. As with the initial inspection that found zero defects, this inspection took 2 hrs, 28 min.
The inspection results verify that the repaired OPC defects are at least equivalent in quality to the original OPC corrections at the defect locations. Since the layout is defect-free, the process window can be extended to detect real marginal features.
Finding marginal features beyond process window
The nine FE conditions matrix is now extended to 17 FE conditions and the FE values encompass the original nine FE conditions with an additional eight FE conditions at values that extend beyond the established process window. The inspection results are summarized in Table 4 and Fig. 6, and the resist image gallery of the 17 FE conditions is shown in Fig. 7.
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The extended process window finds 12,582 CD variation-type defects at two process window corners at ±125nm in focus and +18.5mJ/cm2. The defects are binned into 15 defect categories; 24 defects were found of the type shown in Fig. 7.
 Figure 6. Defect Process Map for extended PW inspection, to accompany Table 4. |
These real, marginal defects at the edge of the process window corners are more sensitive to increased exposure dose and defocus. Using these defect locations, the process engineers are able to monitor these features on wafer for better process control.
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Discussion
These experiments have demonstrated the ability to identify weak pattern defects within the process window, incrementally repair and optimize the OPC, reconverge the optimized OPC back into the layout, and verify that the pattern fidelity is maintained throughout the process window. There are two important points of discussion.
The first point is that if OPC defects are found in the layout with current OPC tools, the OPC recipe needs to be tuned and re-run on the entire layout again. There is a risk of introducing new pattern defects into the layout while correcting and optimizing the tagged defects [2, 4]. A second consequence is the long run-time associated with re-running OPC on an entire layout. Incremental and reconfigurable OPC, because it operates hierarchically on a layout and only optimizes OPC where needed, runs in a fraction of the time of full-chip conventional OPC. This brings us to our second point.
Today, manufacturers use a single OPC recipe for a process or layout. This “one-size-fits-all” paradigm for OPC recipes is likely to change as we move from current production through 90nm to 65nm and beyond. The ability to incrementally optimize and correct OPC where needed and reconverge it back into the layout is a solution for sub-100nm processes. Combining this with the ability to simulate and verify pattern fidelity across the process window gives the user the tools to identify catastrophic failures, CD variations, enclosure defects, and other weak patterns and correct them before the first reticle is ever produced.
Conclusion
In this paper, a way to optimize process windows by combining an incremental and reconfigurable OPC tool with a post-OPC data process window verification solution was presented. The OPC corrections that were incrementally applied to repair the programmed defects are equivalent in quality to the original OPC corrections while saving a significant amount of runtime and reducing the overall data size. Once the OPC corrections were reconverged back into the layout, the FE matrix was expanded to include additional FE conditions where the marginal failures occurred at the edge of the process window corners. The process window could be further increased in focus and exposure by applying incremental and reconfigurable OPC to these marginal patterns and reconverging them back into the layout, creating a more dynamic and robust process window.
References
1. W. Grobman, “Impact of Subwavelength Manufacturing on IC Design and Mask Data Preparation: An Emerging New Paradigm” in Future Fab International 17, 2004.
2. M. Laurance, M. Anderson, M. Pilloff, “Enabling Incremental RET to Exploit Hierarchical Structure across Multiple Designs for Sub-100nm Lithography,” submitted to 25th Annual BACUS Symposium, Photomask Technology, 2005.
3. W. Howard, J.T. Azpiroz, Y. Xiong, C. Mack, G. Verma, et al., “Inspection of Integrated Circuit Databases through Reticle and Wafer Simulation: An Integrated Approach to Design for Manufacturing (DFM),” in Design and Process Integration for Microelectronic Manufacturing III, L.W. Liebmann, ed., Proc. SPIE 5756, pp. 61-72, 2005.
4. X. Wang, M. Pilloff, H. Tang, C. Wu, “Exploiting Hierarchical Structure to Enhance Cell-based RET with Localized OPC Reconfiguration,” in Design and Process Integration for Microelectronic Manufacturing III, L.W. Liebmann, ed., Proc. SPIE 5756, pp. 361-367, 2005.
Melissa Anderson is director of product marketing and business development at Aprio Technologies Inc., 2520 Mission College Blvd., Santa Clara, CA 95054; ph 408/855-8088, e-mail [email protected].
Abhishek Vikram is applications development engineer at KLA-Tencor Corp., 160 Rio Robles, San Jose, CA 95134-1809; ph 408/875 1215, e-mail [email protected].
William Volk is senior director of marketing at KLA-Tencor Corp.
Melody Ma is application engineer manager at Aprio Technologies.
Scott Andrews is senior applications development engineer at KLA-Tencor Corp.
Bo Su is senior applications engineer at KLA-Tencor Corp.