Technology news
05/01/2006
TI and MIT collaborate on subthreshold SRAM in 65nm CMOS
At the recent IEEE International Solid-State Circuit Conference, MIT Prof. Anantha Chandrakasan presented a paper describing the performance of an ultralow power (ULP) (0.4V subthreshold), 256kbit SRAM that was manufactured using Texas Instruments’ advanced 65nm process. The 10 transistors/bitcell SRAM was reported to achieve operation at 400mV and a 2.25× lower leakage power compared to its six transistors/bitcell counterpart at 0.6V (see figure).
According to TI, the SRAM has the industry’s lowest reported voltage and is being considered for the company’s SmartReflex power management technologies that are used to extend the battery life of mobile products. (SmartReflex, announced by TI in Sept. 2005, is a combination of intelligent and adaptive silicon, circuit design, and software used to address power and performance management challenges at advanced technology nodes.)
Dennis Buss, VP, silicon technology development at TI, said that SmartReflex is a way of doing dynamic voltage scaling to adjust the voltage when processing must be done at a very high speed. Explaining IC manufacturers’ challenges, Buss said, “Anyone can scale from the nominal of 1.2V down to about 900mV without doing anything special, but going much below 900mV is a problem-you have to design the circuits in special ways.” TI’s strategy is to scale from 900mV, to 700mV, then 500mV, and eventually, to go below the threshold voltage. The paper by Chandrakasan is a research project with no firm timeline, but Buss estimates that TI should be able to achieve its planned scaling to within subthreshold within the next five years.
Buss maintains that there were no radical process technology breakthroughs necessary to accomplish the work in conjunction with MIT, and no special modifications to TI’s annealing processes were needed. However, he added that in order to get the most out of SmartReflex once the technology moved to the fab, the company had to get the right balance between subthreshold leakage, gate-induced diode leakage, and gate leakage over a range of voltages. Implants did have to be engineered and integration issues with respect to the transistor design had to be addressed.
With the link between process technology development and designers becoming closer and occurring sooner, Buss explained that TI no longer specifies a process at the beginning and then holds to it. Instead, while there are broad guidelines and key unit processes are identified, the process is changing on a weekly basis. Examples he offered of key unit processes and guidelines at 65nm include doing strain in new ways, going to NiSi, and going to a 2.8 low-k OSG dielectric. “But in terms of the details-such as implant doses and oxide thicknesses-all were involved in the trade-offs,” said Buss. -D.V.
Immersion in 2006: The industry is halfway in
The 2006 SPIE Symposium on Microlithography offered an opportunity to evaluate the progress and prospects of liquid immersion exposure at a crucial point, after the R&D stage but before the industry really plunges in. While much of the promise has been realized, the first generations of exposure tools were used mainly to uncover difficulties and perform R&D, not generate revenues. ASML delivered 13 of these systems, converted from dry exposure designs, and many challenges (and steps to overcome them) rapidly became public. Nikon and Canon, meanwhile, built one or two tools and kept the R&D in-house or at a trusted customer. Now, details are coming out.
Nikon, ASML, and some of their customers claim to have achieved similar production-quality defect levels (at least for linear features, if not contacts), and both tool companies are readying production-capable, yet very different, hyper-NA tools.
The ASML XT:1700Fi is built around the familiar Twinscan two-stage platform, with a NA=1.2 catadioptric projection lens and a fourth-generation (“i2”) water nozzle. This nozzle design confines the fluid in the narrow gap above the wafer partly with an air curtain, and incorporates a plug to stop the flow when the stages are changed. In contrast, the Nikon NSR S609B uses an all-refractive lens with maximum NA=1.07 and a continuous flow nozzle with a large water gap, but no air curtain-water is confined by surface tension alone. When a wafer is to be transferred, the lens and nozzle move off to a secondary metrology stage. To minimize thermal aberration in dipole illumination mode, Nikon’s S609B adds a dipole-IR beam rotated 90° relative to the imaging beam. Both the ASML and Nikon systems had to overcome alignment errors due to cooling by water evaporation, but now show sub-12nm overlay errors.
Beyond the new exposure tools, photoresists, resist topcoats, and other materials, processing tracks and process control systems have to be optimized for immersion lithography. Familiar resists used with 193nm dry exposure were not suitable, but many could be made to work when coated with materials to suppress the leaching of species potentially damaging to optics.
Topcoats have to be applied in resist tracks after the resist, then baked and removed after exposure. They come in two flavors: those that dissolve in TMAH resist developer (now becoming standard), and those that require a special solvent. Topcoat hydrophobicity is key, as it controls the angle with the water meniscus. If the angle is too low behind the moving exposure head (receding contact angle (CA) or θr <70°), a water film pulls out, beads up, and forms defects.
 Dynamic contact angles of immersion fluid θa and θr depend on topcoat and stage motion. |
On the other hand, if the meniscus does not slide easily at the leading edge (droplet sliding angle >20° on a tilted wafer), stage speed must be reduced to avoid bubbles (see figures). If a developer-soluble topcoat is too hydrophobic, topcoat removal may be inhibited, which can be especially damaging for contact layers. Resists capable of operating without a topcoat are not yet mature, showing process windows 20% smaller than the best topcoat materials, according to Yayi Wei of Infineon.
 Tilting wafer method to measure dynamic contact angles θa and θr and sliding angle. |
Defects due to the water immersion process were the topic of at least nine presentations. The latest immersion nozzles evidently suppress bubbles effectively, eliminating one defect mechanism that had caused early concern. However, there are other mechanisms that produce the near-circular defects in resist and etch patterns that are thought to be characteristic of immersion exposure tools.
Droplets left behind that are >50µm dia. cause watermarks, partly by leaching out material from the resist underneath, thus changing resist properties (since topcoats are not impervious to water), but also by evaporating, leaving circular deposits of material behind. Topcoat-absorbed water drops can locally alter the heating during post-exposure bake, as can water on the backside of wafers, or create defects under the topcoat. A more serious problem is that flowing water at the edge-bead region can cause topcoat, resist, and BARC materials to de-laminate and wash away, then redeposit on the wafer as noncircular particles. While immersion exposure does add some defects, it reduces the potential for others through increased depth of focus and reduced demands on resolution enhancement technology.
At the Nikon LithoVision meeting, Anita Viswanathan of Tokyo Electron described how immersion challenges were being met in the TEL Lithius i+ resist track. The interface module between the track and exposure tool has been modified to rinse and dry the wafer (front and back) before and after exposure, if needed. Two dedicated robot arms avoid cross-contamination. A predevelopment rinse module dries the wafer from the center out before PEB to avoid re-depositing removed defects, thus reducing the total count from 33 to 1-2/wafer. Similar values were reported by B. Streefkerk of ASML, with pre- and post-exposure soaks.
There likely will be one more generation of exposure tools that use water as the immersion liquid, but then the industry will likely transition to higher refractive-index fluids. These materials are much less aggressive solvents than water, leaching <1/40 of the photoacid generator from uncoated resist material than water does through topcoats. The bad news is that the high-index liquids are much more expensive and have to be recycled. When exposed to oxygen and 193nm radiation, the materials degrade, although not rapidly, according to papers by JSR and DuPont. More than higher index fluids will be needed to keep up with Moore’s Law, according to Kurt Ronse of IMEC: a robust high index material must be developed for the final lens element, too.
So what comes after liquid immersion at 193nm? If the potential of a technology is judged by the funds spent on development, EUV will come next, perhaps beginning in 2009. Hans Meiling of ASML described the progress of their alpha-prototype tool, which has printed 40nm half-pitch lines (a bit smaller than the 1700i), but with a 270nm DOF. Isolated 60nm contacts and 70nm lines were also demonstrated on the full-field system. The collection mirrors for the tin-based source are now predicted to survive for 1-2 years in production. Still, there are throughput, resist, reticle, and infrastructure challenges to overcome if EUV lithography is to be ready for the 32nm node. If it is not, the industry needs a new idea-and quite soon. -M.D.L., E.K.
FSI’s ViPR reaches back to the future of resist strip
FSI International Inc., Chaska, MN, has extended the classic “Piranha” etch/strip wet bath process by creating a point-of-use chemical blending subsystem to equip the company’s Zeta batch spray and spin platform for resist strip. With the goal of 80% of front-end-of-line resist strips at 45-32nm nodes, FSI intends to displace many of the plasma-strip processes currently in use.
Mixing sulfuric acid and hydrogen peroxide results in an exothermic reaction and a corresponding increase in temperature. To achieve 200°C on the wafer, the new technology first raises the temperature of the sulfuric and peroxide streams separately and then mixes them at the right point to achieve maximum reactivity on the wafer surface. This results in a new degree of freedom in working with the classic Piranha chemistry.
The Zeta spray hardware provides an additional degree of freedom, with batches of wafers rotating around spray nozzles while droplets of the ViPR chemistry slide across each wafer’s surface. The moving meniscus of each droplet provides some additional force to assist in cleaning.
A variation on the classic H2SO4/H2O2 (a.k.a. “sulfuric peroxide mixture” or “piranha”) etch/strip process, this process developed for the 45nm node is a return to one of the most basic processes. FSI claims its combination of chemical blending, delivery, and temperature controls enables removal of highly implanted photoresist, including on 1×1017 ions/cm2 plasma-doped photoresist, and reduces underlying material loss by eliminating the ashing step. Initial systems started shipping in March. -E.K.
Tech Brief
Researchers develop foundation for circuitry and devices based on graphite. Graphite, the material that gives pencils their marking ability, could be the basis for a new class of nanometer-scale electronic devices that have the properties of carbon nanotubes, but could be produced using established microelectronics manufacturing techniques, according to research presented at the March meeting of the American Physical Society. Using thin layers of graphite known as graphene, researchers at the Georgia Institute of Technology, in collaboration with the Centre National de la Recherche Scientifique (CNRS) in France, have produced proof-of-principle transistors, loop devices, and circuitry. Ultimately, the researchers hope to use graphene layers less than 10 atoms thick as the basis for revolutionary electronic systems that would manipulate electrons as waves rather than particles, much like photonic systems control light waves.
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