Future challenges in computational lithography
05/01/2006
Today, the errors associated with modeling the lithography process constitute one of the largest error sources in IC manufacturing, according to the modeling and simulation section of the 2005 International Technology Roadmap for Semiconductors. Until recently, full-chip, model-based production computational lithography has focused on performance at the correct or nominal focus and exposure. This process, however, is not perfect.
To the degree that the modeling is inaccurate, the edges on the wafer will end up in the wrong locations. Lithographers tell us that optical proximity correction (OPC) errors and mask errors are their two largest error sources. OPC errors, however, have two components: modeling error and numerical error associated with prescribing the OPC. The fact that OPC is a major source of errors is shocking when you consider that in the recent past, the primary lithography error sources were the mask, the scanner, the resist stack, and the track-OPC didn’t even have a line in the error budget.
As error sources are tackled, it might appear that the reticle enhancement techniques (RET) prescribed by OPC software might work reasonably well at optimum focus and exposure, but if the scanner is slightly out of focus or the wafer is slightly underexposed, the chip may not yield. Due to limitations in computing power, it has not been technically feasible to consider those variables when prescribing or verifying OPC or other RETs.
To prescribe OPC decorations, a computer has to solve the Hopkins’ equation, which describes partial coherence imaging. Solving this equation for a state-of-the-art microprocessor in a way that assumes ideal focus and exposure, as we do today, requires about 10 CPU-years of computing power. Treating focus and exposure as variables would increase the computing requirements by an order of magnitude, to approximately one CPU-century. Even so, in the future, the industry will require “process-window-aware” computational lithography that takes into consideration all the variability that occurs in the normal manufacturing process.
The computing requirements will accelerate even faster as increasing variability is taken into account because several factors are driving computational lithography to consider a new variable: the polarization of the light source. Three-dimensional mask polarization effects come into play as the apertures on photomasks shrink to the point where their widths are nearly as small as their depth and are comparable to the wavelength. The polarization of the light becomes more important as immersion lithography leads to higher numerical apertures. In double dipole exposure, lithographers will use only horizontally polarized light in one exposure and only vertically polarized light in another. Vector imaging, which deals correctly with the polarization and the films that underlie the resist, is becoming critical in computational lithography. To achieve the sub-nanometer modeling accuracy required for the 45nm and 32nm nodes, computational lithography will have to calculate the image at several planes in the resist and then model the 3-D resist development effects.
Computational lithography is just as vital as immersion lithography to the future of the IC industry. The process of applying corrections to every feature of every advanced layer must be correct. The quality of modeling already limits the circuit performance, and the challenges associated with modeling will become more severe in the future.
Today, IC manufacturers run OPC software on systems with hundreds or even thousands of CPUs, and even so, they are compromising accuracy to complete the calculations within an acceptable amount of time. The future challenges of computational lithography will require great advances in computing power or accelerated computing. Fortunately, methods that combine image-based (also called grid-based or pixel-based) approaches with image processing acceleration hardware show great promise in addressing this problem.
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For more information contact Jim Wiley, senior technical director, at Brion Technologies, 4211 Burton Dr., Santa Clara, CA 95054; ph 408-653-4304, e-mail [email protected].