The thin-film landscape for ALD processing
05/01/2006
Different manufacturing requirements for major IC device types call for different thin-film material requirements. Current materials limitations call for higher performing materials solutions. Some incumbent deposition technologies may be extended only to be replaced by ALD at a future insertion node, as driven by device structure and physics needs. Some single-wafer processes will transition to batch platforms and the emergence of “CVD-like ALD” will fill out the process space.
Suraiya Nafis, Jon Owyang, Subrata Chatterji, Aviza Technology Inc., Scotts Valley, California
The industry continues to face many deposition challenges relating to thin-film materials. Each industry segment, based on device application, differs in material and technical requirements, which can be traced to the product technology being served. The logic and memory markets have very different material requirements and integration challenges. While some of the thin-film requirements may be overlapping, each segment seeks unique solutions based on unique technical and manufacturing roadmap timings. Logic, DRAM, and flash segments are all in different stages of atomic layer deposition (ALD) acceptance.
Logic applications
Performance of a logic cell depends on the performance of the transistor itself. In order to improve the performance of logic devices, it is critical for IC manufacturers to reduce gate lengths. The International Technology Roadmap for Semiconductors (ITRS) provides some guidelines in this regard. Table 1 shows an excerpt from the 2005 ITRS for different logic transistor gate lengths designed to serve different applications. For example, high performance gate lengths for microprocessors are expected to remain much smaller than those targeting low standby power for wireless communications.
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Traditionally, device performance increases were a matter of scaling device dimensions. Now, due to the limitations of current materials such as SiOx, new and advanced materials and techniques are required in order to improve device performance from generation to generation.
Currently, IC manufacturers are exploring the following approaches in pursuit of improved device performance:
- inducing strain to increase transistor speed; strain can be either global (wafer level) or local (process strain);
- replacing SiOx gate dielectrics with high-k dielectrics, in combination with bulk Si substrates and silicon-on-insulator (SOI) substrates. High-k films provide lower leakage while maintaining equivalent oxide thickness (EOT) of SiOx. Additionally, using SOI substrates reduces short-channel effects; and
- going from 2D planar transistors to 3D transistors, which enables improved transistor performance through shrinking transistors in a linear direction and adding a third dimension.
Considering the 45nm node as the transition point for a major change in materials or in transistor architecture, it is not yet determined how transistor formation will evolve at the 32nm node and beyond.
One can achieve improved device performance by incorporating strain techniques or scaling. Given the results that can be achieved with both techniques, strain is a more viable manufacturing option today, thus delaying the need for scaling and the use of high-k materials at current generations. Strain technology has already been implemented at the 90nm node and is anticipated to be extendible to the 65nm node. It’s important to note that strain Si technology improves device performances but does not increase device density.
High-k gate dielectrics. It may be that, at or below the 45nm node, strain technology alone would not be enough to improve the device performance to the required level, so shrinking the gate length is necessary. As previously mentioned, gate length shrinking along with reduced gate dielectric thicknesses comes with inherent challenges of excessive leakage currents and short-channel effects.
It is obvious that materials with lower leakage currents and equivalent capacitances are needed to reduce gate leakage currents due to the quantum mechanical tunneling of charge carriers through thin SiOx gate oxides. Thicker high-k dielectrics of the same EOT are possible replacements of SiOx or SiON gate dielectrics to reduce leakage currents. EOT can be expressed as:
where kSiOx is the dielectric constant of SiOx, kx is the dielectric constant of the high-k dielectric material, and tx is the physical thickness of the high-k film.
The higher the dielectric constant, the thicker the film and the lower the leakage would be to replace the SiOx films. The most extensively studied high-k dielectrics are AlxOy, TaxOy, ZrOx, HfOx, and their derivatives. To date, Hf-based dielectrics are considered to be the most promising to replace SiOx or SiON gate dielectrics.
Once the high-k dielectrics are chosen, a secondary issue occurs with the poly-gate electrodes. High-k dielectrics and poly electrodes are not compatible due to Fermi level pinning, chemical instability, poly depletion effects, and boron diffusion through the high-k dielectrics. High-k dielectrics necessitate the use of dual-metal electrodes with proper work functions, one for N-type and the other for P-type transistors. This again adds up to the complexity of process integration and device manufacturing processes. The metal electrodes under consideration are TiN, Ru, TaN, and silicides such as NiSi, HfSi, etc. Below the 45nm node, ALD will be the dominant technology to deposit high-k gate dielectrics and metal gate electrodes because of superior control of composition and thickness.
Integration is another hurdle for implementation of high-k dielectrics with metal gates. Desirable high-k films may be either single-crystalline (epitaxial deposition) or amorphous, but polycrystalline structures cause higher leakage currents through grain boundaries. Conventional process flows require high temperature (~1000°C) source/drain dopant activation anneal after gate formation, and IC manufacturers have been developing high-k dielectrics that can withstand such a high-temperature anneal process.
Some manufacturers are already contemplating using HfOx with fully silicided (FUSI) electrodes at the 45nm node for low operating power logic applications by modifying the process flow to a gate-last process. Gate-last process flows avoid exposing HfOx to high temperature (~1000°C) source/drain dopant activation anneals. In gate-last flows, gate films are deposited inside an area defined by gate spacers, and must have near 100% step coverages. At the 32nm node, the aspect ratios of the gate structures will be >5. ALD will be the choice of deposition technique especially for gate-last processes, due to its ability to deposit highly conformal films.
For low operating power devices, where leakage current requirements are very stringent, it will be necessary to use thicker high-k dielectrics using metal electrodes. However, high performance logic would most likely continue with SiON gate dielectrics with metal electrodes.
Replacing planar with 3D transistors. At the 32nm node, the gate length is projected to be only 13nm, and the short-channel effect translates into reduced and uncontrolled threshold voltages. Some planar transistors with high-k dielectrics, metal electrodes, and strained channels technology do not have significantly reduced gate lengths. However, transistors built in a vertical direction, where gate electrodes are wrapped around a thin Si fin for example, have better threshold voltage control, higher drive currents, and are also scalable.
Manufacturing challenges currently remain. The thin fins of Si must be coated uniformly with gate dielectrics and electrodes. Given the structure of these fins, ALD will be the choice of deposition technique for gate dielectrics and electrodes.
DRAM applications
The need for constant refreshing of DRAM capacitors to overcome the inherent loss of charges slows down device performances. For acceptable device performances, capacitance needed per capacitor is 30±5fF, according to the ITRS.
The motivation behind shrinking cell sizes is to increase memory density and thus to reduce cost per bit. To maintain the same capacitance values with shrinking device sizes, DRAM capacitors evolved into two segments: trench capacitors and stack capacitors. Each segment carries a different set of manufacturing challenges and film technology requirements.
Trench capacitors. Total capacitance values are maintained by increasing the capacitor areas and decreasing the capacitor dielectric thicknesses. Expanding capacitor area is accomplished by increasing the depth of capacitors farther into the Si and by making the trenches bottle shaped. Hemispherical Si grains are also used to roughen the trench walls to further increase the surface areas as shown in Fig. 1a. At the 65nm node the aspect ratio of the trenches is ~80:1. Coating these structures uniformly requires near 100% step coverage, which is a challenge.
 Figure 1. Schematic of a) trench capacitor and b) stack-capacitor DRAM cells. |
At the 45nm node, the aspect ratio will be greater than 100:1. In order to retain the same capacitance values, high-k dielectrics and metal electrodes will be necessary. Trench DRAM capacitors are formed prior to transistor formation. This adds another demand on the high-k dielectric to withstand the high temperature (~1000°C) dopant activation anneal process during the transistor formation steps. The potential high-k dielectrics are AlxOy, HfSiON, HfSiN, TiOx, etc. and metal electrodes TiN, Ru, etc. We expect ALD to be the de facto deposition technique due to the 100% step coverage in high-aspect-ratio structures. Other deposition techniques, such as MOCVD, are capable of coating similar trenches only when the aspect ratio is 40 or less.
Stack capacitors. Unlike trench capacitors, stack capacitor structures cannot increase in area to compensate for any reduction in capacitance (Fig. 1b). Consequently, stack capacitors have already made the transition to high-k dielectrics in order to keep the capacitance values the same. Stack capacitors are created after transistor formation, making it easier to identify high-k dielectrics with less restrictive temperature requirements. In pursuit of better step coverage, the stacked capacitor DRAM manufacturers have already embraced ALD using high-k dielectrics such as AlxOy, TaxOy, HfOx, and ZrOx for capacitors and TiN for the metal electrode. At 65nm or 45nm nodes, even higher-k dielectrics will be needed, possibly TiOx and metal electrode Ru.
Flash applications
Over time, two dominant flash memory cells have evolved: floating gate with a poly-Si trap layer and SONOS, which uses an insulating trap layer. At the 45nm node, both floating gate and SONOS structure cells face severe scaling issues.
 Figure 2. Schematic of a floating gate flash memory cell. |
In floating gate flash memory cells, for example, the interpoly dielectrics that separate floating gates from the control gates also coat the vertical sidewalls, thus increasing the interpoly dielectric capacitances (Fig. 2). Higher capacitances across the interpoly dielectric (compared to those across the tunnel oxide) are needed for effective charge trapping in the floating gates.
The universally accepted way of increasing bit density is to scale down the devices. However, this poses issues for flash memory cells at 45nm node, such as decreased interpoly dielectric capacitances and the interference between cells.
 Figure 3. Flash memory interpoly dielectric thickness scaling at 45nm, as per the 2005 ITRS. |
Adjacent cells at the 45nm node are too close for the interpoly dielectric and the control gate to coat the sidewalls of floating gates, as shown in Fig. 3. This reduces interpoly dielectric capacitances. Materials such as SiOx/SixNy/ SiOx cannot keep the floating/control gate capacitance-coupling ratio the same, thus a higher k dielectric will be needed. Another reason for high-k insertion at the 45nm node is that the thickness necessary to trap charges in floating gates is >12nm. The ITRS calls for EOT much less than 12nm, so the transition to high-k dielectrics is aligned with this requirement.
To control the interference between cells, high-k dielectrics must replace SiOx, SixNy, and SiOx. Currently, the most suitable films are AlxOy, HfOx, and HfSiOx.
Film deposition methods
The three main methods for depositing thin films are physical vapor deposition (PVD), chemical vapor deposition (CVD, including metal organic CVD or MOCVD) and ALD, as shown in Fig. 4. Potentially, any one of these deposition methods is capable of depositing high-k materials and metals.
 Figure 4. Pressure and temperature domains inside of which different thin-film deposition technologies operate. |
The higher the deposited film surface smoothness, the better the reliability. Smoother surfaces do not allow local electrical fields or point defects. Threshold voltage control, which is critical for logic transistors, requires stringent film composition control. For DRAM and flash applications, ~100% step coverage is needed. As illustrated in Table 2, ALD satisfies all these requirements better than CVD/MOCVD or PVD.
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ALD fares better then the incumbent technologies in all counts except for relative throughput (Fig. 5). Substantial improvements in throughput have been achieved by the entry of batch ALD solutions in this space, increasing throughput by 2-4×. Batch systems are challenged with meeting the same film properties as single-wafer systems that have established the ALD process over the last few years. Therefore, innovative gas distribution such as in Cross Flow technology helps to create a single-wafer environment around each wafer in a batch system, resulting in highly uniform films (within wafer, wafer-to-wafer, batch-to-batch). Film properties are comparable to that of single-wafer tools. DRAM capacitor dielectrics and electrodes, as well as flash interpoly dielectrics, are good candidates for batch ALD.
A batch system is not a solution for applications requiring subsequent layers to be deposited without breaking vacuum, such as gate stack. Gate-stack deposition may also require plasma pre-clean before films deposition. Therefore, gate stack will be expected to be deposited using single-wafer ALD systems. To improve throughput, a pseudo-ALD mode could be used where the deposited films will have some CVD components in them without degrading films properties. Throughput could be improved at least 2-3× compared to pure ALD films. To achieve lower cost of ownership, tool manufacturers will have to pay close attention to reducing the cost of tool operation by employing innovative optimized chamber designs to minimize precursor usage, increase tool up-time, etc.
Conclusion
Improved IC performance requires shrunk devices geometries. With scaling comes the challenge of coating higher-aspect-ratio devices, limiting the types of deposition techniques available that can achieve the proper requirements. When scaling is required, there are two issues that challenge IC manufacturers: the thinning of current materials that have reached their physical limits, and higher aspect ratios with smaller dimensions. Therefore, new materials development is critical in order to complement advanced deposition techniques such as ALD. Current technologies such as MOCVD and PVD will also be challenged to extend their capabilities and will ultimately meet their limitations. ALD illustrates that it has the ability to deposit new materials with the right properties, while ensuring film uniformity and conformal step coverage.
Suraiya Nafis received her PhD in physics from the U. of Nebraska-Lincoln. She is a senior product marketing engineer in the ALD Business Unit of Aviza Technology Inc. Previously, Nafis was a field process engineer at Genus Inc. (now Aixtron AG) and a senior process engineer in both GaAs and Si wafer fabrication areas. Aviza Technology, 440 Kings Village Rd., Scotts Valley, CA 95066; ph 831/439-6258, e-mail [email protected].
Jon Owyang received his BS in chemistry from the U. of California, Berkeley. He is director of ALD product management at Aviza Technology Inc. Previously, Owyang was a senior strategic enabling engineer at Intel Corp. and also held technology development positions at LSI Logic and Philips Semiconductor. He holds five patents related to process technology.
Subrata Chatterji received his BA from the U. of Calcutta, India, his MA from the U. of Bombay, India, and his MBA from the U. of San Francisco, CA. He is VP and GM of Aviza’s ALD Business Unit. He has more than 14 years of experience in marketing, strategic business development, operations integration, and general management. In prior positions, he was head of ASML Thermal’s ALD Business Unit and was ASML’s director of strategic business development.