Annealing techniques for optimizing 45nm-node USJs
05/01/2006
Various p+ extension implantation dopant species and annealing techniques (spike, flash, laser, and SPE) were investigated to achieve high dopant activation and low damage ultra-shallow junctions (USJ) 15-20nm deep for 45nm-node applications. Because of their wide temperature range for dopant activation without diffusion, it was discovered that using molecular dopant species (B10H14 and B18H22), and either high-temperature (flash or laser) annealing, or low-temperature solid-phase epitaxial (SPE) annealing, proved very promising for the 45nm-node process integration with SiON or high-k Hf-based dielectric gate-stack structures.
John Borland, J.O.B Technologies, Aiea, HI; Akira Mineji, NEC Electronics Corp, Sagamihara, Japan; Wade Krull, SemEquip, Billerica, MA; Masayasu Tanjyo, Nissin Ion Equipment, Kyoto, Japan; Robert Hillard, Solid State Measurements, Pittsburgh, PA; Tom Walker, Accent Optical Technologies, Bend, OR
For the 45nm node, the p+ USJ for extension varies from 15nm-20nm deep, depending on the device application and trade-offs between dopant activation, junction depth (Xj), and junction quality for high performance (HP), low operating power (LOP), and low-standby power (LSTP) logic devices. To minimize boron dopant diffusion, high-temperature annealing at >1300˚C (flash or laser) or low-temperature (650˚C SPE) annealing is available, resulting in 0-5nm of dopant movement.
To eliminate dopant channeling, pre-amorphization implantation (PAI) is usually used. PAI and/or co-implantation also lead to higher dopant activation. However, the residual end-of-range (EOR) damage from PAI or co-implantation techniques leads to high damage junctions when using these advanced dopant activation techniques for minimal dopant diffusion. For this reason, we investigated alternative p+ dopant species, such as B10H14 (B10) and B18H22 (B18), because of their self-amorphization effects that enhance dopant activation, while avoiding EOR damage resulting in high activation, low-damage, and high-quality junctions [1].
Another benefit of using molecular dopant species is the ability to extend beam-line implantation for several more device generations beyond the 32nm node by avoiding decel-mode implantation (energy contamination) and spot-beam blow-up effects that have been reported to result in gate length (LG) and threshold voltage (VT) variation, as well as asymmetrical transistors [2].
Since the boron solid solubility (Bss) limit in silicon is usually 10-100× lower than the chemical dopant level at the surface, the annealing system determines dopant electrical activation level, and across-wafer uniformity mirrors the anneal signature. For these reasons, new metrology techniques are needed to optimize 45nm node USJ processes, and those techniques are showing the unique signatures of both the implanter and annealing process.
Experiments
Boron 500eV/1E15/cm2 dose equivalent implants were performed on one hundred, 200mm, n-type wafers using B (500eV), BF2 (2.5keV), B10H14 (5keV), and B18H22 (10keV) implant species, with implantation done at NEC, Nissin, and SemEquip. The implants were made into crystalline silicon or amorphous silicon using Ge 5keV/5E14/cm2 for PAI. Both batch and serial implanters were used for implant signature comparison.
Dopant activation was achieved using: 1) spike annealing at 1080˚C, or at 1000˚C at Mattson/Germany, 2) msec flash annealing at 1300˚C at Mattson/Canada, 3) sub-melt 200 nsec laser annealing at Sopra, and 4) 650˚C 5 sec SPE annealing at Mattson/Germany. Electrical measurements were made by both contact and noncontact methods for dopant activation, junction depth, and junction quality measurements. Sheet resistance (Rs) was measured with a noncontact junction photovoltage (JPV) method at Frontier, and a contact, nonpenetrating 4-point probe (4PP) using elastic material (EM) probes at Solid State Measurement (SSM), and both mercury (Hg) probes and blunted probes at Four Dimension (4D).
The electrically active surface dopant level/density was measured by a C-V technique called Nsurf at SSM. Secondary ion mass spectrometer (SIMS) analysis was used to determine the boron chemical density depth profile, and cross-sectional TEM (X-TEM) was used to evaluate the amorphous layer depth and after-anneal residual implant EOR damage. After-anneal junction quality was determined by junction leakage measurement using JPV at Frontier. Silicon crystal lattice damage levels were also measured by photo-luminescence (PL) imaging at Accent on as-implanted and after-annealed wafers.
Results
SIMS boron (10B and 11B) dopant depth profiles were measured on all the samples. Due to channeling into crystalline silicon, the B case has an Xj of 26.9nm at 1E18/cm3, while the Xj for the B18H22 case is at 19.7nm. With Ge-PAI, the B case has an Xj at 17.9nm, while the B18H22 case has an Xj at 16.6nm. Table 1 shows all the Xj SIMS chemical junction depths, all the conditions studied, and the amount of dopant movement-either positive or negative-after each annealing technique. A shallower Xj occurred for some of the diffusion-less activation cases. Figure 1 shows the various amounts of B dopant movement (diffusion) for the B18H22 activation/annealing techniques into both crystalline and amorphous silicon.
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 Figure 1. SIMS results for the B18H22 cases showing various amounts of dopant movement for several activation techniques into a) crystalline, and b) amorphous silicon. |
As listed in Table 1 and illustrated in Fig. 1a, with 1080˚C spike annealing, 25nm of diffusion occurred; with 1000˚C spike annealing, 5.7nm of diffusion occurred; with flash annealing, 0.3nm of dopant movement; with laser annealing, there was 1.3nm of dopant movement; and with 650˚C SPE annealing, there was -0.3nm of dopant movement. If the junction depth was defined at 1E19/cm3, the flash and laser dopant movement results would be the opposite with 1.5nm for flash and 0.1nm for laser. PL analysis was used to get a full wafer map of the as-implanted damage and damage recovery (residual implant damage) after annealing, as shown in Table 2 for arbitrary PL units (APLU). The APLU data clearly show complete implant damage recovery (low APLU values <16) for the wafers receiving the 1080˚C and 1000˚C spike anneals, as well as the flash anneals. However, all of the PAI laser-annealed wafers still showed high APLU values of 55-64, suggesting that a high level of residual implant damage remained.
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 Figure 2. X-TEM for B18H22 wafers showing: a) 6.2nm self-amorphous layer, b) SPE with no EOR damage, c) laser with no EOR damage, and d) flash with no EOR damage. |
The BF2 wafer without PAI had a post-laser anneal APLU value of 27, suggesting residual EOR damage. This value was similar to the APLU value observed for the 650˚C SPE annealed samples with PAI, B and BF2. Only the B10H14 and B18H22 wafers showed APLU values that indicated complete damage recovery. X-TEM analysis on selected B18H22 and Ge-PAI+B18H22 wafers are shown in Figs. 2 and 3, which provide better interpretation of the PL results. The B18H22 (B18) implant created a 6.2nm deep self-amorphous layer (Fig. 2a), while the Ge-PAI created an 11.5nm-deep amorphous layer (Fig. 3a).
After flash annealing, the APLU values were 9, and the X-TEM showed no residual implant damage (Figs. 2d and 3d). With laser annealing, the B18 wafer APLU was 13, and the X-TEM was clean (Fig. 2c). Also with laser annealing, the Ge-PAI+B18 wafer APLU was 55. The X-TEM in Fig. 3c shows an 11.5nm-deep amorphous layer remaining, which indicates that no recrystallization occurred. With SPE annealing, the B18 APLU was 14 and the X-TEM of Fig. 2b was clean, while the PAI+B18 wafer APLU was 29 and the X-TEM of Fig. 3b shows EOR damage 12nm deep.
The unique signature of each annealing technique can be seen by full-wafer PL imaging. Spike annealing shows a center-to-edge gradient with the highest APU (10.3) in the center and 9.2 at the edge; flash annealing shows dark spots (8.1APLU) where the wafer lifters are located (an artifact of the earlier version of the tool used to process the wafers) compared to the other bright areas (7.7APLU); the SPE signature is slightly darker towards the center (35.9APLU) compared to the edge (32.4APLU); and laser annealing shows a step and repeat checkerboard pattern.
 Figure 4. Wafer striping PL image from a scanned laser annealer. |
Figure 4 shows both full-wafer PL imaging for macro-mapping; localized imaging for micro-mapping of another laser-annealed wafer with a scanning motion (rather than a step-and-repeat motion); a spot size of ~5.5mm; and 0.41mm of overlap (Fig. 4). So PL analysis provides very good macro and micro sensitivity for mapping slight variations in non-uniformities.
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Junction quality/damage recovery was characterized by JPV RsL leakage measurement. The results are shown in Table 3 (A/cm2), and all the spike and flash annealed samples-with or without Ge-PAI-had junction leakage <1E-7A/cm2 (measurement sensitivity limit). As shown by X-TEM (Fig. 3c) and detected by PL (Table 2), the Ge-PAI wafers with laser annealing remained amorphous and the RsL measured leakage was in the E-2 to E-3A/cm2 range. B18, B10, and B were in the 1-3E-7A/cm2 range, and BF2 was 3E-6A/cm2, which suggests residual EOR damage that was also detected by PL with an APU of 27.
Results for the SPE anneal showed an excellent junction leakage current of 2E-7A/cm2 measured for the B10 and B18 wafers, suggesting high-quality junctions. The Ge-PAI wafers were in the E-5A/cm2 level. The B and BF2 wafers were in the E-5 and E-6A/cm2 range, which also suggests EOR damage after SPE annealing and was also in agreement with the PL analysis results. X-TEM analysis of the SPE-annealed B wafer (not shown here) clearly showed defects (not EOR damage) throughout the first 5.5nm in depth. Additional X-TEM analyses are scheduled in the future. Good correlation between RsL junction leakage current to PL arbitrary units (APLU) was observed.
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For shallow junctions <25nm deep, an accurate 4PP sheet resistance (Rs) measurement for dopant activation is very difficult to obtain due to probe penetration of any or all of the probes. Therefore, we compared several new alternative methods to measure Rs (Ω/sq.). Nonpenetrating contact EM-4PP and Hg-4PP Rs results, as well as JPV Rs results are compared to standard 4PP with blunted probe tips (Table 4). For most of the conditions, good agreement between all the various Rs metrology techniques were verified. However, for some of the conditions, a wide range of Rs values were observed, especially for the B laser and SPE diffusion-less activation anneals even though SIMS analysis detected deep junctions of >24nm.
 Figure 5. Rs vs. Xj for B dopant activation level determination. |
From the Rs vs. Xj plot (Figure 5), the dopant activation level was determined [3], however, since there is always uncertainty in the true electrical junction depth, as well as the measured Rs value by each of these techniques, there is uncertainty in the true activated level. The determined dopant activation level, which is also known as the boron solid solubility limit (Bss), is listed in Table 5.
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The wide spread in Bss values for a specific annealing technique is due to the wide range in Rs values determined by the various metrology techniques listed in Table 4 and seen in Fig. 5. PAI+B with a 1000˚C spike anneal Rs determined Bss varied from 0.5-1E20/cm3 and for PAI+BF2 with an SPE anneal, Bss varied from 2.5-5E19/cm3. For this reason, a new technique to directly measure the near surface electrically active dopant density (Nsurf) within the top 3nm of the surface was developed using an EM-probe CV based technique. Using this technique, we could directly measure the surface-activated dopant density, and therefore compare each implant species and annealing conditions without having to know the electrical junction depth.
Table 5 also shows Nsurf results. The highest Nsurf dopant activation levels were seen with pulsed laser annealing (1.6E20/cm3) followed by flash (1.2E20/cm3), and then spike annealing (7.5E19/cm3), and SPE (7.4E19/cm3). For each annealing technique, the highest dopant activation was always detected for the molecular dopant species without Ge-PAI, while the opposite conclusion would be made using Bss determined for the Rs vs. Xj data in Table 5. Except for the SPE annealing case, the Bss values were similar, with or without Ge-PAI for the spike and flash anneals. For SPE anneals, the Ge-PAI wafers always had higher Bss activated levels.
Conclusion
High-quality and high-dopant activation p+ junctions ~15-20nm deep can be achieved using B10H14 or B18H22 with high temperature (>1300˚C) flash or laser annealing, as well as low temperature SPE annealing at 650˚C. These anneals enable the extension of beam-line implantation to beyond the 32nm node with energies at 5-10ke V. Therefore, molecular dopant species are very attractive for SiON gates using fast (msec) or ultra-fast (200nsec) annealing, or high-k Hf-oxide gates requiring low thermal budget processing.
Each advanced annealing technique for diffusion-less activation has a unique signature as revealed by the PL wafer map imaging analysis that must be optimized for the best activated dopant uniformity. However, metrology to determine the activated dopant level for these diffusion-less techniques is still subjective and needs improved accuracy and repeatability, especially to determine the true electrical junction depth for the Rs vs. Xj plots. The Nsurf technique could provide this information in the future through beveling measurements.
Acknowledgments
The authors are grateful for the support from Seiichi Shishiguchi of NEC, Dale Jacobson of SemEquip, and Wilfried Lerch, Silke Paul, Jeff Gelpey, and Steve McCoy of Mattson Technology for the spike, flash and SPE anneals; Julien Venturini of Sopra for the laser anneals; Michael Current and Vladimir Faifar of Frontier for RsL measurements; Mark Benjamin of Solid State Measurements and Andrzej Buczkowsk, Zhiqiang Li, and Steve Hummel of Accent for PL analysis; and James Chen of Four Dimensions for Hg-probe Rs analysis.
References
- J. Borland, M. Tanjo, N. Nagai, T. Aoyama, D. Jacobson, “Applying Equivalent Scaling to USJ Implantation,” Semiconductor International, p. 52, Jan. 2005.
- T. Aoyama, M. Fukuda, Y. Nara, S. Umisedo, N. Hamamoto, M. Tanjo, T. Nagayama, “Decaborane Ion Implantation for Sub-40nm Gate Length PMOSFETs to Enable Formation of Steep Ultra-shallow Junction and Small Threshold Voltage Fluctuation,” IWJT-2005, section S2-2, p. 27, June 2005.
- J. Borland, T. Matsuda and K. Sakamoto, ”Shallow and Abrupt Junction Formation: Paradigm Shift at 65-70nm,” Solid State Technology, p. 83, June 2002.
For more information, contact John Borland, the founder of J.O.B. Technologies, at 98-1204 Kuawa St., Aiea, HI 96701; e-mail [email protected].