Technology News
04/01/2006
IBM and JSR show immersion lithography can be pushed beyond 32nm
IBM, JSR, and JSR’s US operation, JSR Micro, have printed 29.9nm patterns to provide proof-of-concept that high-index materials can extend immersion lithography beyond the 32nm node. Researchers used JSR’s organic fluid with an index of 1.64, its regular high-volume 193nm dry resist with an immersion top coat, and a high-density crystal quartz prism with a 1.67 index in IBM’s two-beam interference exposure tool, improving on both the 1.44 index of water and the 1.56 index of the usual lens to demonstrate that extending resolution to future nodes is possible.
Using the higher-index fluid leaves the lens as the weakest link in the exposure system. The research version is not a viable alternative for production, since the crystal elements align and leave a signature effect, and the birefringence would be uncontrollable.
Other issues remain, but researchers say progress has been fast and encouraging. The high-index organic compound is sensitive to oxygen and will need an effective recycling system. Mark Slezak, JSR Micro technical manager for lithography, notes that some sort of creative showerhead is needed to blanket the fluid with nitrogen. JSR is working on developing a recycling system to deal with the organics that get into the immersion fluid over time from photodecomposition and leaching of the resist.
 Sub-32nm lines made with JSR’s high-index fluid. |
How quickly is the fluid likely to degrade? “We just don’t know yet,” says Slezak, since it’s not yet clear what sort of flow rates will be used. But he notes that static studies of decomposition of the material in a quartz cell exposed to intense light look promising. “The rate of change is very low,” he says. Costs don’t appear to be a major issue. “We feel we are well within the $1/wafer that the industry is asking for,” he contends.
JSR also has developed a new second-generation high-index fluid, a slightly different organic molecule that has a slightly higher index of refraction (1.65), but appears to better protect the resist. “Early defect and leaching numbers coming out are lower than water-an order of magnitude different from water,” says Slezak. Thus the new version appears to protect the resist and could potentially work without a topcoat. It also improves transparency to 99.4%, higher than water’s 99.3%.
JSR is now ready to ramp volume production of its resist topcoat for immersion use.
The best high-index lens material so far seems to be lutetium aluminum garnet, with its index of 2.1, according to Nikon’s Tomoyuki Matsuyama. However, its transmission is only 4%/cm, whereas the industry needs >98%. It also has a birefringence problem that’s apparently worse than calcium fluoride, and that was enough to sink 157nm lithography. - P.D.
Tohoku U., Selete, NIST show neutral particle beam limits plasma damage
Tohoku University, Selete, and the National Institute for Advanced Industrial Science and Technology (AIST) have demonstrated devices made with Tohoku’s low-damage neutral-particle beam plasma etching process that exhibit significantly reduced leakage and improved electron mobility.
In conventional plasma processes, stray particles and photons that bombard the surface can build up troublesome charges in fine patterns and create damage at nano-order geometries that can affect device performance. Tohoku’s process reportedly prevents much of this damage by converting the charged particles into neutral ones and blocking the emitted light (Fig. 1).
 Figure 1. Neutral-particle beam plasma process reduces damage from charged particles, light, and heat. (Courtesy: Tohoku U., Nikkei Microdevices) |
Previous attempts to make neutral particle beams have relied on neutralizing the positive ions by accelerating them and colliding them with gas molecules to change the charge. But the acceleration requires several hundred eV of energy, and the conversion process is not very efficient, so the resultant beam is low density and high energy. This means processing is slow and not very selective, so the technology hasn’t been practical for production processes.
Instead of neutralizing the positive ions, Tohoku U. neutralizes the negative ions to make its neutral particle beam. Stripping electrons off the negative ions takes much less energy and is highly efficient. The equipment is based on an induction-coupled plasma tool, with carbon electrodes for ion acceleration added above and below the quartz chamber. Depending on the polarity of the voltage applied to these carbon electrodes, either positive or negative ions can be accelerated. Tohoku creates a pulse-modulated plasma suitable to create negative ions, with pulses on the order of microseconds. Gas is showered in from the upper electrode, and ions accelerated from the plasma are neutralized as they pass through 1mm diameter, 10mm deep apertures in the lower electrode.
When a negative bias of -200 to -800V is applied to accelerate the negative ions, the neutralization rate is close to 90%. By using the negative ions, the process produces a low-energy, highly efficient neutral-particle beam.
Tohoku used these soft, neutral F and Cl beams to etch a 50nm gate structure, a 32nm node finFET, and sub-10nm structures.
Working with Selete, Tohoku used a SF6/Cl2 gas plasma to make a neutral F/Cl beam and etch a 50nm polysilicon gate structure, and compared gate oxide damage and gate leakage to conventional plasma etching. To improve processing precision, etching speed was held to 30nm/min and the beam energy was controlled, improving the etching selectivity ratio for the first gate oxide layer to 100:1.
Though the neutral-particle beam etching still showed some antenna effect, leakage current was an order of magnitude lower. With a low electrical field of 5MV/cm, leakage dropped from 10-4 to 10-5 A/cm2 with an antenna ratio of 400, or from 10-3 to 10-4 A/cm2 with a ratio of 20,000.
 Figure 2. Neutral-particle beam etches silicon sidewall to atomic-level flatness (left) and leaves less damage than conventional reactive ion etch (right). |
With AIST, Tohoku made a finFET for the 32nm node with the low-damage method. Though non-planar transistors may help solve off-state leakage problems at 32nm, the tiny 3D structures have proved difficult to fabricate with precision. A TEM photo of the upright channel etched with the neutral-particle beam process shows atomic-level flatness of the silicon substrate, and almost none of the plasma-induced damage of the conventional plasma etching (Fig. 2). As a result, electron mobility was about 30% better, approaching its ideal theoretical level, and enabling lower-power operation.
Tohoku also used the technology to etch 7nm diameter nano-dots with Matsushita Electric Industrial and the Nara Institute of Science and Technology. Conventional etching processes typically have trouble making precise structures below about 10nm because of plasma damage, leading researchers to look to problematic self-assembly methods instead. But by using a ferritin mask with an Fe core and a Cl-based neutral particle beam, anisotropic etching of high-aspect ratio 7nm columns was demonstrated. - Seiji Samukawa, Tohoku University, SST partner Nikkei Microdevices
Freescale touts mobility gains with new GaAs MOSFET
Freescale Semiconductor has developed a device combining a gallium arsenide (GaAs) semiconductor with traditional metal-oxide semiconductor field-effect transistor (MOSFET) technology, citing the better mobility of GaAs as well as its scaling capabilities, which are on par with traditional silicon materials.
At the heart of Freescale’s research is a new oxide film (Ga2O3) that passivates the semiconductor surface of a GaAs wafer and unpins the Fermi level (comparable to what silicon dioxide does on a silicon wafer), so that the bulk and surface characteristics of the material are identical. The fabrication technique utilized a high-temperature effusion cell in an MBE reactor, with deposition temperatures as high as 1800°C and a crystalline source material inside the effusion cell. The resulting GaAs device has a mobility of about 6000cm2/V-sec, about 20× the mobility of a comparable Si device. The proprietary film stack is the equivalent of a high-k material (k~20), thereby enabling very high-speed circuits with little or no leakage.
Freescale’s efforts are reminiscent of work done by Lucent a decade ago depositing films on GaAs wafers, but those films could not provide functional MOSFETs, said Karl Johnson, Freescale senior technical Fellow and director. “The oxide that was put down [in the Lucent study] didn’t totally passivate and unpin the Fermi level at the surface of the semiconductor,” explained Johnson. “Hence, there was no intrinsic mobility in the material.”
The key to the development, according to Matthias Passlack, technical member in Freescale’s microwave and mixed-signal technology lab who was involved in the original Lucent work, is understanding which oxide unpins the Fermi level out of the many different oxides that exist. “Some very basic science needed to be done, and interactions needed to be understood at an atomic level to make the correct film choice and determine the correct deposition methods,” he said.
The work is still in the R&D phase, but the team believes it may be possible to achieve limited production capacities in two or three years. The initial target application is in wireless communications for enhanced performance in power amplifier functions as well as very high-speed portions of circuits in large signal applications and RF applications.
Other benefits are anticipated for optoelectronics, in which recombination at the surface of III-V optodevices tends to affect the efficiency of the device. By using the new film, the Freescale team hopes to passivate the surface and either minimize or completely eliminate the recombination at the surface of the device, as well as enhance the III-V devices’ optical and electrical performance.
With respect to future digital applications, the researchers believe the technology will complement Si at the sub-45/32nm nodes, and possibly at the 22nm node. - D.V.
Brion Technologies enters OPC implementation market
Brion Technologies, a leader in resolution enhancement technology (RET) verification, has announced its new Tachyon OPC+ product that applies optical proximity correction (OPC) to chip designs using the company’s computational lithography technology. The Tachyon OPC+ avoids the tradeoffs characteristic of previous rule- and model-based RET technologies and provides the lowest cost at a given speed and accuracy, according to Jim Wiley, senior technical director of Brion.
Like previous RET-verification offerings sold to customers such as from the Crolles-2 alliance and NEC, OPC+ is a calibrated software application that runs on the company’s proprietary Tachyon platform with its hardware acceleration, high-speed bus, and grid-based sampling. Each rack costs several million dollars, and one or two racks can be used to tackle OPC verification. However, OPC rendering takes more computing power, so up to four racks have been considered and quoted to customers for memory and logic applications. “This is a 65/45nm solution for people who are squeezing everything that they can get out of their existing lithography processes,” explained Wiley.
The OPC implementation market is larger and more diverse than the OPC verification market that previously had provided the bulk of Brion’s recent business growth. Still, the Tachyon OPC+ would be used at tape-out by the same computational lithography group that is responsible for RET and DFM in most companies. There are now companies that have twice as many people in computational areas compared to more traditional aspects such as scanners, resists, etc.
The input for the computational lithography group is the “designer intent” layout to which OPC decorations (or more challenging RET technologies) must be applied. The mask set with RET is then verified across the predicted process window by the verification tools and taped-out to a mask house for fabrication. The input parameters for the Tachyon model at the core of both the OPC+ and verification tools come from extensive measurements on calibration wafers printed using proprietary masks.
The Tachyon hardware/software system flattens designs down to the single level of an array of pixels, instead of retaining information in a vector-based modeling space. So the modeling is inherently image-based or pixel-based, instead of vector-based or polygon-based, and the performance of Tachyon and the new OPC+ application is insensitive to design hierarchy, pattern density, and file size. Consequently, the run-time for OPC+ scales linearly with the die area, and the run-time can be precisely predicted and managed as part of the design cycle.
Brion claims that competing technologies that retain hierarchy while applying OPC require longer run times, and are inherently unpredictable. For example, a customer using a previous OPC technology required weeks-to-months to render a single mask layer of a microprocessor, while three parallel Tachyon racks could do the same job in an hours-to-days time scale.
Tachyon OPC+ has evidently been tested at TSMC and other Brion customers that implement OPC for their own and their customers’ designs. Dr. Burn Lin, senior director of micropatterning technology at TSMC has been quoted as saying, “With Tachyon OPC+, we have the power to achieve excellent OPC quality with fast and greatly predictable cycle time at our site.”
While this new technology certainly represents an improvement in the accuracy and convenience of RET implementation, it does not, by itself, solve the DFM dilemma. Designers still have the option to create conflicts and suboptimal structures in their layouts. Processes can still drift in the time between characterization and production.
The greatest strength of Tachyon OPC+ may also be the greatest weakness: the flattening of the design hierarchy. Information is inherently lost when the design is flattened into a single layer of pixels, and some of the lost information may involve the original “design-intent.” Of course, it is only another step to the inherent flattening of mask fabrication, so it may be acceptable to lose hierarchy information at OPC implementation. The promised lower costs and run-times may be well worth the trade-off in lost hierarchy. Lithography engineers -computational and otherwise-will be dealing with such issues for a long time. - M.D.L., E.K.
New CMP pad optimized for copper barrier removal
Chemical mechanical planarization (CMP) processes often must balance ultimate planarization against induced defects. Typically, any change to CMP that improves planarization tends to induce additional defects. For example, the polishing pad employed in the process may be made more rigid so that it conforms less to the underlying geometry and thus increases planarization, but rigid pads tend to induce defects such as scratches.
Most CMP of copper barrier layers currently uses soft-pads, but ever-reducing geometries mandate reduced topography variation, so Rohm and Haas Electronic Materials has created a new pad technology designed to improve planarization without inducing additional defects.
Barrier CMP processing includes the removal of unwanted barrier material (typically TaN/Ta), dielectric films (such as oxide caps), and in some cases anti-reflective coatings (such as silicon nitride). The company claims that the new pad, the VisionPad VP3100, incorporates specially engineered polymers that combine the benefits of both hard and soft polishing pads and are compatible with industry standard CMP slurries for barrier removal processes.
To achieve the planarization requirements, the pad stack was manipulated to provide different top and subpad physical properties, and the grooving pattern on the top layer was optimized. The top layer uses the engineered polymer with reduced hardness to reduce defects such as scratches, while the subpad layer provides overall mechanical rigidity.
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A renewable topside pad surface ensures consistent removal rate throughout the life of the pad and minimizes nonuniformity and defect generation. Hard pads are renewed through diamond conditioning. Soft-pad conditioning is typically not an option, due to the high pad wear rate caused by diamond conditioning reducing pad life to unacceptable levels. The VisionPad, unlike standard soft pads, allows for diamond conditioning to create a renewable surface without resulting in excessive pad loss.
An Applied Materials Mirra CMP tool was used with a Lam Synergy scrubber to test the new VisionPad. All wafer processing and measurements were performed in a class 10 clean room environment. The polishing process used a three-platen configuration: platen 1 for copper planarization, platen 2 for copper clearing, and platen 3 for barrier clearing and topography correction. The pads used for copper polishing were IC1000 family pads on platen 1 and 2, and VisionPad VP3100 on platen 3 using Politex and IC1000 pads as controls for the VP3100 results. The slurries used for the polish testing were Rohm and Haas Electronic Materials slurries. The wafers used in this study were 200mm 15KÅ electroplated blanket copper and 200mm copper pattern 854 TEOS wafers. The defect measurements were taken at 5mm edge exclusion using a 0.20μm detection threshold, and included continuous scratches, chatter scratches, and skipping scratches.
Polishing rates of the barrier, copper, and dielectrics using the new pad technology can show different results than those achieved with standard commercial pads. Slurry pH, particle type, percent particles, and proprietary additives interact differently with the pad’s surface texture. These differences show up as shifts in removal rates, particularly the relationships between material removal rates known as selectivities. In general, the copper and dielectric removal rates and selectivities resemble those seen with a soft pad, while removal rates for barrier materials such as TaN appear more like those for a hard pad. Process adjustments can be used to fine-tune the removal rates and selectivities to the desired levels.
Figure a shows that the defect performance of the new pad is similar to that of standard soft pads on copper blanket wafers; hard pad scratch levels are typically several orders of magnitude higher than those from soft pads. The planarization ability of the new pad is compared to the standard hard and soft pads in Fig. b. The soft pad conforms to large features and continues to remove copper and dielectric, resulting in reduced planarization and increasing total metal loss. The new pad, like the standard hard pad, does not conform to these features and is able to selectively remove the barrier and dielectric to reduce topography and minimize total metal loss. This technology is intended to meet industry performance needs in 65nm technology cycle CMP processes. - E.K.
Tech Briefs
Clean nanolayers of silicon are efficient conductors - Until now, scientists believed that ultra-thin layers of silicon were poor conductors of electricity because of charge trapping at the silicon/native oxide layer surface. However, researchers at the University of Wisconsin-Madison and wafer supplier Soitec USA have found that silicon layers just 10nm thick will conduct electricity efficiently, provided that their surfaces are clean, as reported in the journal Nature. The team discovered that it could image a 10nm-thick boron-doped silicon layer in a scanning tunneling microscope, a feat that is only possible for a good conductor. The silicon layer was supported on a silicon dioxide substrate, creating a silicon-on-insulator (SOI) system. The silicon portion of such a system grows an oxide layer on its surface when it is exposed to air. Removing this native oxide layer with germanium increased the silicon layer’s conductivity and enabled the imaging process. The researchers believe that the cleaning process creates new electronic states on the silicon surface. These surface states interact with the bulk band structure of the silicon, enabling high-mobility carrier conduction and boosting conductivity. Conductivity at the nanoscale was independent of the amount of dopants added to the silicon. The team expects that silicon nanomembranes could have applications in high-speed electronics and novel sensors.
New gallium nitride film method beats the heat - A team of Los Alamos National Laboratory scientists has developed a method for growing crystalline gallium nitride (GaN) films at lower temperatures than industry standards. By eliminating the higher temperatures and harsh, reactive environments that limit the types of materials used as substrates, the discovery could greatly increase the use of crystalline GaN films in optoelectronic devices, such as blue LEDs and laser diodes, high-density optical data storage devices, flat-panel displays, and solid-state lighting. In research published recently in Applied Physics Letters, the team describes its use of energetic neutral atom-beam lithography/epitaxy to grow crystalline and polycrystalline GaN films on bare c-axis-oriented sapphire at temperatures between 100 and 500°C using low kinetic energy nitrogen atoms and a simultaneous flux of gallium metal. Energetic neutral atom-beam lithography, or ENABLE, is a Los Alamos system that produces a beam of neutral atoms with low kinetic energies that can be used for various kinds of specialized surface chemistry at near room temperatures, often producing results that are unattainable using other techniques.