Encrypting process information for litho-aware OPC models
04/01/2006
Bob Naber, Wolf Staud, Cadence Design Systems, San Jose, California
The practice of using design rules to communicate manufacturing capability to the design community failed with the advent of sub-wavelength imaging’s recommended and suggested design rules. That’s because it is practically impossible for a designer to implement all these rules. Therefore, design for manufacturing (DFM) below the 65nm node requires a new level of two-way communication between design and manufacturing to address the explosion in number and type of design rules.
One of the key aspects of a DFM work-flow is vertical integration. Some foundries are essentially integrated device manufacturers (IDM) with over-capacity and great process knowledge and expertise. Pure-play foundries now realize that leading-edge IDMs offer some advantages. The success of an IC company, especially a fabless IC company, going into manufacturing at the 65nm node and below, will largely depend on the level of vertical integration it can practically establish.
To implement models, some means of communication needs to be established. In the past, established design rule manuals (DRM) ensured that a design was design-rule-check (DRC) clean and, therefore, met all the manufacturing requirements. However, complex process-design interactions mean that this approach is no longer viable. A shift to model-based implementations-model-based OPC, model-based RET, model-based DRC, etc.-is required at 65nm and below.
Two-way communications
A new bi-directional transfer vehicle is needed to implement the communication between design intent and manufacturing capability. A one-way vehicle is no longer sufficient. Many examples exist in today’s tape-out world of designs getting stuck at maskmaking, or even worse at some wafer manufacturing step. The communication challenge between the design and manufacturing communities is enormous, since the high level of specialization in each field has resulted in individuals who now speak different languages. A designer usually does not understand, and may not desire to learn, about chemical mechanical polishing (CMP), etch, and lithography factors such as numerical aperture, sigma, and wavelength. The manufacturing engineer is in a similar situation regarding design attributes such as critical timing analysis, area analysis, and extraction.
When a wafer or lot is put on hold or fails in the fab, the process engineer does not have the information needed to determine if the reported defect harms the functionality of the device and if it should be completely scrapped. Much time and material are wasted because of this lack of input.
Similarly, re-occurring manufacturing variations in CMP, etch, deposition, and lithography that affect yield hardly ever get reported back to the design world. The real problem is in marginal layouts, that is, those with yield-limiting features that depend on the day-to-day, run-to-run variability in an average wafer fab.
What the industry needs is a vehicle to enable this two-way communication seamlessly across the language and culture barriers of design and manufacturing. This vehicle, or file, needs to contain the process model of manufacturing, which can be proprietary, and to be transported to run securely in the background infrastructure of the design community.
Process model files
This process model file (PMF) contains lithography and process settings, such as NA and measured illumination pupils used for determining actual OPC/RET models, SB rules, and calibrated OPC/RET model parameters, as supplied by manufacturing. The PMF allows for different levels of encryption so that the process settings and OPC parameters are unusable without a proper key as issued by the manufacturer. The encryption also allows for a high level of abstraction of complicated manufacturing and lithography process parameters that designers neither want nor need to know (Fig. 1).
It is essential that all tools in the design and manufacturing areas are able to both read a PMF and, in the development stage, write a PMF. The OPC tool must have the capability to deal with all types of OPC/RET masks and handle image decomposition for double exposure types. Most important, the tool must handle the re-combination and interactions of these layers, and provide accurate and fast modeling.
Consider a chromeless phase lithography (CPL) mask as an example. To best model CPL printing behavior, it is critical to be careful in capturing the inherent 2D patterning distortion resulting from a strong proximity effect. Hence, it is necessary to calibrate the OPC model with actual 2D resist patterns to ensure the desired accuracy of the model.
The PMF and the manufacturing know-how it describes is crucial intellectual property. In order to maintain direct and open communication from manufacturing to design, all of the proprietary manufacturing information must be well protected. What’s needed, therefore, is a PMF that can describe realistic OPC models, but cannot allow for the retrieval of actual process settings and model information.
PMF in the design flow
IC designers need to verify their designs at two stages: at the layout design stage, where interactive checking is necessary, and at the DRC stage, where full-chip manufacturing verification is required. Different groups at various stages of design have different levels of access to the PMF, and therefore different keys. When a reliable OPC model is applied, designers can visualize the severe 2D pattern distortion that inevitably occurs after OPC treatment. The pattern can be exercised throughout varying process conditions, and different OPC/RETs can be applied. Thus, the original design manufacturability can be interactively improved by adding and revising OPC implementation in an environment where electrical design intent is maintained.
Performing a full-chip DFM verification before taping out to the mask shop has increasingly become a standard practice since the 90nm node. As shown in Fig. 2, the verification goal is to quantify global errors, such as floating polygons (printed resist residues), feature edge misplacement (CD error or 2D pattern distortion), and line-end shortening (end cap).
Only the designer truly knows what was designed into the circuit. Unfortunately, when converting a layout design to GDS at tape-out, all of this information is lost. A better approach is to work with databases that preserve design intent. In so doing, it is possible to re-establish vertical integration, with the last check being a step undertaken in the same design environment as a sign-off in parallel to DRC.
Bob Naber is the product marketing director for RET products in the DFM group at Cadence Design Systems, 2655 Seely Avenue, San Jose, California 95134; ph 408/428-5120, e-mail [email protected].
Wolf Staud is product manager of RET Solutions at Cadence Design Systems, where he is responsible for RET solutions within the DFM organization.