Chipmaking’s tough economic road ahead
03/01/2006
Semiconductor manufacturing is entering a new phase. While great attention is being paid to coming technology challenges, the economics may prove even trickier.
Over the next few years, two major factors will force changes in fab manufacturing models. One is the rise of myriad consumer and mobile devices with shortening life cycles. The other is the need to reach optimum power/performance design trade-offs without the benefits of traditional scaling.
The miracle of steadily lower cost/function with shrinking IC features, propelling existing markets and creating whole new ones for huge volumes of mass-produced chips, has worked for a half century. Today, the leaders in microprocessors and memory chips - Intel and Samsung - are thriving as this progression continues. But key market drivers are changing. Even Paul Otellini, Intel’s CEO, at the recent Consumer Electronics Conference (Las Vegas, Jan 5-7), admitted that “…we are at the end of the PC era.” Actually, a strong market will remain for PCs, especially in developing nations, but it will not be as dominant as it was in the past.
So what comes next? Many thought it would be “convergence” on an integrated electronic center including the PC, TV, and gaming that would include broadband access for entertainment, communications, and information. While this may happen, a much bigger driver - called “personal technology” by Brian Halla, CEO of National Semiconductor, at the recent Semi Industry Strategy Symposium in Half Moon Bay, CA - is taking shape. This will look more like proliferation than convergence.
Halla broke industry history into eras with four different main drivers: mainframe computers in the ’70s, PCs in the ’80s and ’90s, connected PCs/cell phones starting about 2000, and then a combination of a host of devices (DVD, PDA, PVA, LCDTV, HDTV, notebook PC, full-feature handsets, and more) over the next few years. Live video of traffic on a major artery in the Bay area illustrated the type of new application Halla believes will create essentially “infinite” demand for personal technology. He predicted that a mobile wireless mesh network will allow a user to access broadband information from anywhere by the end of this decade from a terabyte-storage pocket device more powerful than today’s PCs.
Life cycles for these proliferating electronic gadgets are shrinking from years to months as a stream of new, cooler models emerge. Thousands of diverse chips in limited lots with short life spans will be needed to meet the demand.
Further, at the recent IEDM in Washington, DC, Mark Horowitz, director of Stanford’s computer systems lab, presented an analysis done with Stanford co-workers, Intel, and IBM showing that the best way to reduce power drain in future megachips would be to tune designs more to specific applications.
The dilemma for the industry is that the design costs for a new microprocessor could run $20-100 million, Horowitz pointed out, not counting the escalating costs of complex mask sets.
How can the industry shift from mass-producing millions of standard devices to processing thousands of small lots of specialized chips with short life spans, while keeping costs down for the consumer market? Megafabs running large wafers may still be the most cost-effective way to make chips, but many innovations will be needed to allow them to nimbly process thousands of designs at high throughput, high yield, and low cost, on short cycles.
Although the challenge seems daunting, solutions are already taking shape. Some chipmakers are making fabs more agile, with quicker set-ups and yield ramps. Libraries of well-tested cores are being expanded so they can be combined on chips, sometimes along with some programmable logic for different applications. Multichip package stacks are growing, with progress on R&D for through-chip vias and bump technology so that all contacts do not have to be at the chip edges. Multiproject wafers used for prototyping at foundries might provide a way to spread small lots over many wafers rather than just a few. Automated wafer handling systems and fab control software is becoming more adept at productively handling many small runs. Even greater collaboration between fabs, process tool and automation developers, and packaging and assembly engineers will be needed for success. Let’s make it happen.
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Robert Haavind
Editorial Director