Technology News
03/01/2006
Intel demonstrates 45nm SRAM test chip right on schedule
Intel says it has demonstrated the first working 45nm chip, keeping the company right on pace with its two-year development cycle, and right on schedule to begin its 45nm microprocessor product ramp in the 2H07. “Typically, we demonstrate the test chip in the first quarter of the even numbered years, and begin the CPU product ramp one and a half years later. So far 45nm is on track for the same series of events,” said Mark Bohr, Intel senior fellow and director of process architecture and integration.
The functional 153Mbit SRAM test chip shrinks the six-transistor memory cell size to 0.346μm2, about half the size of the 65nm cell, continuing the doubling of transistor density every two years. Intel says it also improves the performance per watt, cutting transistor switching power by >30%, and either improving switching speed by >20% or reducing leakage power by >5×. The shuttle test chip includes two 153M SRAM units, some of the key logic circuits that will be used in eventual microprocessors, and other structures to test various parameters.
Intel is saying little about the technology involved except that all the basic design rules and processes are locked down, and most if not all of the manufacturing tools are decided. The critical layers are all made with 193nm dry lithography, and while Intel is not using any exotic finFETs or tri-gate transistor structures, Bohr notes the company is “doing innovative things with both transistor and interconnect materials.”
Intel continues to use the much-simplified SRAM cell layout developed for 65nm. This layout replaces bi-directional gates with all horizontal ones and replaces wrap-around diffusion features with all vertical ones with smooth edges. This allows much more efficient packing of features into the space with only limited actual scaling of pitch for easier manufacturability. The former approach would mean that the 65nm SRAM cell area would be reduced 40% from the 90nm version with only ~5% scaling of the pitch of the first metal layer. - P.D.
Protein guides nanocrystal self-assembly for flash memory floating gates
An improved method for nanocrystal placement for the floating gate of a flash memory cell, using a protein-mediated self-assembly approach, was described at the 2005 IEDM conference by Shan Tang, U. of Texas, Austin. A template formed by a chaperonin protein lattice can be used to place nanocrystals of different types in a regular array at high density from a colloidal suspension, according to Tang and her co-workers.
Chaperonins are large multimeric structures with two stacked rings having a central cavity into which proteins bind. The interior of the cavity is hydrophobic, so that nanocry tals combined with hydrophobic molecules can be trapped inside cavities measuring 4.6nm dia. with 4.5nm walls for the protein used in the experiments. The chaperonins can be self-assembled into a crystal lattice on a silicon surface through noncovalent interactions between them, as shown in the figure. Experiments showed that cavity size could be varied to provide a potential nanocrystal size filter using magnesium or potassium ions or ATP (adenosine triphosphate), Tang explained. After the nanocrystals are uniformly distributed at high density, the protein is removed by annealing.
Nanocrystals or quantum dots between the control and tunnel oxide in flash memory cells are being explored because they promise to greatly extend retention time while avoiding leakage from any weak spot across the tunnel oxide (electrons are stored at specific sites, rather than across a film). They also might operate at lower power at higher speed with longer lifetimes.
The experiments with PbSe (lead selenide) and Co (cobalt) nanocrystals were done with chaperonin 60 (GroEL), the most studied chaperonin protein, with Co showing the best storage retention. This was expected since a metal provides a higher density of states so that more electrons can be stored at each site. The protein is commercially available, according to Tang. The authors conclude that flash memories could be fabricated with the protein-mediated self-assembly process for floating gates using any existing nanocrystals. - B.H.
Polymer tunnel diodes enable both logic and memory functions
Low-current density resonant tunneling diodes (RTD) were shown by J.P.A. van der Wagt in the paper, “Tunneling-based SRAM” (Proceedings of the IEEE, Vol. 87, Issue 4, April 1999), and all subsequently published work used compound semiconductors. Now, just as compound semiconductor LEDs have inspired research into organic LEDs (OLED) for different applications, compound semiconductor RTDs have inspired the development of organic variants for low-power memory and logic circuits.
Researchers Woo-Jun Yoon, Sung-Yong Chung, and Sita M. Asar, working with Ohio State U. professor Paul R. Berger, have demonstrated polymer tunnel diodes (PTD) based on conjugated polymers first developed for OLED manufacturing. These organic-based semiconductor structures can provide the possibility for room temperature memory and logic. Current-voltage measurements show large and reproducible negative differential resistance (NDR) with a peak-to-valley conductance ratio (PVCR, indicating the potential signal integrity) as high as 53 at room temperature.
However, these new PTDs require - in addition to the semiconducting polymer layer - a uniquely structured TiO2 layer to function. The TiO2 was formed by low pressure (~10-7 torr) Ti PVD, followed by oxidation in an inductively coupled plasma (ICP) reactive ion etch (RIE) system with O2 plasma at RF power of 80W and the substrate at room temperature for 24 hrs. Conversion to TiO2 was monitored using AFM and ellipsometry, and the final films showed ~2.2 refractive index. As deposited Ti thicknesses (prior to oxidation) of 2, 4, 6, and 8nm were tried, and the first three all show strong NDR effect; the 8nm TiO2 sample was not fully oxidized as seen by film ellipsometry and by large leakage current (presumably through residual metallic regions) in diode structures.
As seen in Fig. a, the researchers used the poly[2-methoxy-5-(2’-ethyl-hexyloxy)-p-phenylene vinylene] (MEH-PPV) as the polymer molecule. MEH-PPV is commercially available as a material for OLED applications. The 0.5% polymer in solution (80% toluene and 20% tetrahydrofuran) was spin-coated, and then soft-baked at 60°C for 24 hours to create films nominally 25nm thick.
 a) Chemical structure of MEH-PPV; b) flat-band energy diagram showing how the tunneling can occur; and c) the PTD structure in cross-section. |
The MEH-PPV with the special TiO2 layer, along with an indium tin oxide (ITO) anode and an aluminum cathode, combine to create the complete semiconductor diode. The flat-band energy diagram (Fig. b) shows how the tunneling can occur, while Fig. c shows the PTD structure in cross-section. The substrates were glass coated with 10 Ω-cm blanket ITO, while the Al cathodes were produced by PVD through a simple shadow mask. The formation of the TiO2 layer seems to be critical for the RTD effect.
Two control structures were built with different film stacks to examine the possible mechanisms behind the NDR effect seen with ITO/TiO2/MEH-PPV/Al: no TiO2 layer, and replacing TiO2 with Poly(3,4-ethylenedioxythiophene) poly(styrenesulfonate) (PEDOT:PSS = a conductive polymer used in OLED structures). Neither exhibited NDR in the bias range of -10 and 0 V, indicating that the observed NDR in the MEH-PPV structure cannot be due to either electron trapping in the ITO, or metal spikes at the anode/polymer interface. The tunneling mechanism is suspected to be more complex than that across a thin TiO2 barrier, since the peak current density does not decrease with increasing TiO2 thickness over the range of 2-6nm starting Ti thickness.
Additional support for the theory that tunneling does not simply occur through the thin TiO2 barrier was found by experiments with more complete Ti oxidation. Using 400°C with the O2 plasma treatment resulted in more thorough conversion to TiO2, and diodes built using this layer did not exhibit the NDR effect. Thus, the effect is hypothesized to result from local defect sites within the TiO2 film.
The new PTDs can be used to form TSRAM cells for memory, and a single JFET along with two RTDs can be configured to function as a monostable-bistable transition logic element (MOBILE) latch. Logic based on MOBILE latches should allow for very low power-consumption.
The pronounced NDR using a thick polymer layer with a large active area, instead of molecularly sized junctions, seems promising for manufacturing. However, the defect sites within the TiO2 layer must also be repeatably and controllably formed, and it seems unlikely that 24-hour cycle time for a unit-process step could be acceptable for volume production. Still, this shows proof of concept for manufacturing advanced logic circuits independent of a silicon substrate. - E.K.
Japanese project simulates imprinting, generates masks from device data
Japan’s national MEMS (microelectromechanical systems) project reports development of software tools for MEMS devices that can simulate nanoimprinting results under different process conditions, and can automatically generate a mask set, starting from the desired device structure.
The development effort is one of a series of Japanese government funded projects, under the auspices of the Micromachine Center, that aim to make it easy for everyone to create MEMS products, to assure Japan a strong position in that growing market. The three-year, $10 million (¥1.2 billion) MEMS-ONE project targets strengthening Japanese resources in software and design, where even the largest local supplier, Mizuho Information and Research Institute, lags US market leader Coventor in market share.
The simulation tool draws from a detailed database of materials characteristics, developed by Nagoya University professor Kasuo Sato, to simulate how variables like heat, pressure, time, and light intensity will affect the impression imprinted by the mold. The software can then determine the best combination of parameters for resolution and throughput, for imprint systems using either heat and pressure or UV-cured resin. However, the program apparently cannot yet deal with the changes to the pattern made by pulling the mold off the substrate.
Another module of the system automatically generates the mask set for a given device structure. Instead of starting with the mask and running a simulation to see if it in fact makes the desired pattern, this tool works in reverse, starting with the desired final pattern, and then generating the etch mask, resist mask, and the photomask patterns needed to create it. It also reportedly selects the optimal combination of etch mask and process to create a given pattern.
There are, however, some problems to be worked out when a government-funded research effort develops such a potentially commercial product. Developers say they aim to release an alpha tool in mid 2006, and a commercial version in early 2007, when the three-year project winds down. The nine participating companies will have free access to the IP developed, and Micromachine Center will distribute an initial free version of the software. Some sales system will likely have to be worked out to fund future support and upgrades.
Since the project was funded by tax dollars, it seems likely it will be available only to Japanese users and only with a Japanese-language interface. But even some Japanese MEMS suppliers are asking for an English version, so their engineers outside Japan can use it, too. And the software could not likely become an industry standard without an English version. - SST partner Nikkei Microdevices
New metal etch process targets flash and DRAM
Applied Materials recently released an upgrade of its DPS II technology, called AdvantEdge Metal Etch, at Semicon Japan to take advantage of a growth in applications using flash memory - especially NAND flash. The new technology targets both flash and DRAM, according to Neil Hanson, director of etch business management at Applied.
 a) 65nm logic TiN HMO; and b) 70nm M1 DRAM with a hard mask. (Source: Applied Materials) |
Applied’s Axiom resist strip chamber, used in conjunction with the metal etch chamber, increases the amount of active oxygen to boost the strip and passivation rates after metal etch. By increasing the amount of oxygen instead of merely increasing the wafer temperature, higher rates are achieved without engendering nonremovable resist residues, which occur at high temperature.While logic drives back-end-of-line (BEOL) technology, flash memory is recognized as the technology driver for front-end-of-line (FEOL), including applications such as USB drives and MP3 players.
In addition to the targeted applications in flash and DRAM (see figure), Hanson sees a potential boon from companies’ increasing use of a metal hard mask (HM) for dual damascene (vs. a multilevel resist scheme or other HM scheme). “The metal HM approach may gain traction because it has been found to eliminate issues with resist poisoning,” he said. “If it takes off, it will be a very large market for metal etch, because there could be as many as nine metal levels on a wafer vs. only two or three levels for Al etch.” - D.V.
Seiko Epson makes flexible SRAM by transfer from glass to plastic
Seiko Epson reports making an SRAM on a flexible plastic substrate and reading it with a thin film transistor made on the same sheet, potentially opening the way for actual flexible electronics modules combining processors or displays with memory.
Though other organic TFTs have previously been made on flexible substrates, the low heat tolerance of the plastics means the devices had to use amorphous silicon to keep process temperatures below 200°C, resulting in devices with threshold voltages that varied too widely to be read reliably. So instead, Seiko first makes the transistors on a glass substrate for processes up to 400-500°C, allowing the use of polysilicon for higher quality devices with less threshold voltagevariability. After the transistors are made, they are taken off the glass and attached to a plastic substrate. A sacrificial layer of polysilicon between the active region and the glass is used and then removed with a laser to separate the transistors from the original substrate.
The company made an SRAM cell of six thin-film transistors for 16K of memory, and a read-out circuit on a 200μm plastic substrate. It read the output in 200 nsec (at 6V). Gate length was 3μm, and the cell area was 68 × 47.5μm. - SST partner Nikkei Microdevices