Wafer-level final test costs driven by MCPs and SIPs
03/01/2006
Bruce J. Barbara, FormFactor Inc., Livermore, California
Industry pundits have said that the current semiconductor cycle is being driven not by PC sales as in years past, but by a portability revolution featuring new mobile consumer electronics. Mobile systems such as cell phones and MP3 players integrate imaging, communications, and computing functions into smaller, more portable sizes. In these price-sensitive systems, expensive systems-on-chips (SOCs) are out, and cost-effective multichip packages (MCPs) and systems in package (SIPs) are in. The advantages to using these packaging schemes are that they move testing upstream into the production process, which can enhance yield, and they simplify testing of packaged, known-good die (KGD).
But space conservation comes at a price. In contrast to a year-on-year decrease in capital equipment cost and cost per transistor, packaging has shown little change in price. As consumer electronics assemblies become more complex and more highly integrated, packaging can sometimes exceed the cost of the chip. Packaging is clearly a candidate for cost reduction - and manufacturers can be expected to take steps sooner than the industry might think.
SOC vs. SIP
From cell phones to MP3 players and from USB drives to flash memory cards, portable technology is getting smaller. The race to shrink dimensions and weight has produced smaller features such as displays, keypads, and smaller spaces in which to house the electronics that drive the devices.
Manufacturers are discovering drawbacks to SOCs as they continue to push the envelope on device performance and size. SOCs typically incorporate a logic-computing element with a reasonable amount of memory to support it, and even a radio frequency (RF) element. However, there are physical limitations to the miniaturization of SOCs.
In addition, when both memory and RF components are required, they can undermine SOC performance with their conflicting requirements. While RF requires a higher voltage, greater memory capacity demands more complex architecture. For processing applications requiring more than one or two megabytes of information, SOCs can prove a sub-optimal solution.
In contrast, SIPs combine individual chips that perform one or more functions. Cell phones are appearing with packages that incorporate a baseband processor, dynamic random access memory (DRAM), and even NAND and NOR flash memory chips, such that anywhere from four to six die are stacked in one tiny footprint.
FormFactor research shows that the discrete package component is becoming more expensive relative to the overall component cost. For SDRAM, package cost typically represents about 7% of device revenue. That cost nearly doubles for DDR2 packages, and more than triples in DDR3 packages, accounting for about 25% of revenue (Fig. 1).
In some cases, the package may exceed the cost of a semiconductor chip itself. For example, with each generation of DRAM, increased performance has required more power and ground pins as well as a larger ball-grid array, driving up the cost of every aspect of assembly, from materials to capital equipment. In a sense, cost is proportional to pin count. While SIPs mitigate this issue to a certain extent, SIP cost is influenced by individual chip yield. In packaged systems, yield is based on the respective viability of each of the chips in the package. A high yield rate for four chips can be lowered significantly by a poor yield rate for a fifth one. That compounding effect is prompting manufacturers to look for ways to improve yield.
Wafer-level final test benefits
There are a couple of options for addressing the cost of SIP. One route is to eliminate the package and opt for semiconductors affixed directly to the printed circuit board.
Another route is to test more chip functions before packaging. After that, memory chips are difficult to test individually and impossible to repair or replace, since comprehensive, bare-die testing - that is, after the wafer has been diced - simply is not feasible. Although some of the industry’s efforts are directed at evaluation techniques that reconstruct wafers from good chips, or that put chips in a special carrier for assessment, these approaches have yet to prove reliable and cost-effective.
The testing that has proven most promising takes place while the chip is still in wafer form. Rigorous assessment of performance under conditions equivalent to or in excess of the kind of performance expected from the final package identifies KGD. Support is growing for pushing testing upstream in the manufacturing process, and semiconductor test and equipment companies are working to make the process more cost-effective for manufacturers.
Wafer-level burn-in (WLBI) makes it possible to conduct burn-in tests early in the manufacturing cycle and identify failures that might otherwise emerge later in the field. Furthermore, any damage caused under these conditions has the potential for repair and product recovery, which can increase overall yield. Burnout or breakage that takes place during assembly, package test, or in the field is irreparable. The loss of an entire package rather than a chip is more costly as well.
By moving testing upstream in the production process, manufacturers enhance yield in several other ways. Early insight into reliability and performance helps product engineers refine design. Adjustments can be made to fabrication before thousands of chips have been packaged, instead of weeks after they’ve been sent for outsourced assembly. Once KGD are packaged, manufacturers need only perform fast, simple open/short tests, using a lower performance tester, or even fully depreciated testers for greater test throughput and cost reduction.
Rethinking test
 Figure 2. Multiple chip sorts can incur damage from the force of probe contact. |
The device test industry has begun to introduce advanced technology for final test at the wafer level. Relevant wafer-sorting capabilities (in excess of the needs of semiconductor and system packagers that can be key) include:
- high-bandwidth specification for at-speed testing;
- cross-talk measurement <10% of signal amplitude;
- signal skew specification, pin-by-pin if possible, to allow for critical timing specifications to be tested and for facilitating speed binning at sort;
- high parallelism, to test as many die with the fewest touchdowns possible, for faster throughput;
- accelerated temperature testing, up to 150°C and down to as low as −40°C, ideally using the same probe-card architecture;
- high-current capacity; for example, Intel discussed a test design capable of 1.7A of current through one probe [1]; and
- low-impact probing, to minimize the physical effect of multiple chip sorts (Fig. 2).
Ultimately, semiconductor manufacturers must determine the “sweet spot” of test requirements for wafer-level final test. At the recent Southwest Test Conference, Elpida discussed the results of a test of DDR2 product performance gauged at 667 Mbs that determined a high correlation between package and wafer-level at-speed test [2]. Without a doubt, the advent of SIP architecture and the specter of rising package costs are going to require manufacturers and system packagers to re-think the role of device test in production. In doing so, they’ll reap the benefits of faster throughput, better device yield, and a stronger bottom line.
References
- Matt Claudius, “SIU Probe Burn Control,” Southwest Test Workshop Proceedings, June 5, 2005.
- Masahide Ozawa, “DDR2 DRAM High-frequency Test at Probe (HFTAP),” Southwest Test Workshop Proceedings, June 6, 2005.
Bruce J. Barbara received his BSEE degree from the U. of Arizona and has more than 25 years of experience in memory design and technical management including DRAM and high-speed SRAM products. He is director of memory engineering at FormFactor Inc., 7005 Southfront Rd, Livermore, CA 94551; ph 925/290-4186, e-mail [email protected].