Fueling innovation with virtual re-aggregation
03/01/2006
Jan Willis, Cadence Design Systems Inc., San Jose, California
Disaggregation of the electronics design chain, along with industry-wide collaboration, is here to stay. However, as industry expertise remains distributed among myriad players across the globe, companies are being challenged to work together in new ways to meet their design and manufacturing objectives. But will the need for collaboration negatively affect innovation, as some believe? Or, as industry disaggregation continues to escalate, will companies learn to become experts in horizontal slices of the vertical design chain? We believe that in this new environment, companies are finding ways to achieve virtual re-aggregation to meet design and manufacturing challenges - without sacrificing innovation.
The emergence of a new diagonal routing architecture, known as X Architecture, serves as an example of the positive role that collaboration can play in the development of new technology. The X Initiative, comprising more than 40 global entities across the design chain, anticipated the need for a collaborative effort to accelerate the commercial availability of its solution in silicon manufacturing. Such an effort would have to span the entire design chain - in this case, to bridge the disparate worlds of electronic design, mask fabrication, lithography, and chip production. The lessons learned offer a useful framework for future collaboration between design and manufacturing entities in the silicon design chain. Three strategies formed the basis of the effort.
The first strategy involved minimizing changes to the design chain in order to keep barriers to adoption low. The X Architecture was defined to preserve the existing investments in cell libraries, memory cells, memory compilers, and other intellectual property (IP). This was achieved by retaining Manhattan-based interconnect routing in design layers 1 through 3, where such IP is typically found. This backward compatibility came as a pleasant surprise to the industry and accelerated adoption by the IP providers.
The second strategy, at the other end of the spectrum, was the development of a whole new family of X-based, design implementation products. For the new architecture to be adopted, the design software needed to deliver significant value over the Manhattan alternative. The collaboration was able to demonstrate that the X Architecture can reduce wirelength up to 20% and vias up to 30%.
In between these two ends of the spectrum, a set of basic design chain enablers was identified as necessary to create the “whole product.” So the third strategy in our framework was to provide early proof points and education to facilitate the development and deployment of these whole product components. In the case of the X Initiative, chip fabrication companies such as TSMC and UMC developed a new set of test structures and test chips to create new X design rules and X-aware OPC/DRC rule decks.
The impact of the initiative’s efforts has been demonstrated by the successful collaboration of ATI, Cadence, and TSMC, which recently delivered a high-performance PCI Express graphics processor for desktop and notebook computers. The ATI device was implemented using the Cadence X Architecture design solution and manufactured on TSMC’s 0.11μm process. This X-based implementation eliminated one metal layer from the original Manhattan-based design, increasing performance, reducing die costs, and enhancing profitability.
The collaborative framework used by the X Initiative and employed by its members serves as a model for how future challenges at 65nm and beyond can be met, including the next generation of low-power techniques and the ongoing challenges associated with nanometer lithography. Successful players in this evolving landscape will learn to collaborate in new ways, realizing competitive advantages through alliances with open development partners.
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For more information, contact Jan Willis, senior VP of industry alliances, at Cadence Design Systems Inc., 2655 Seely Ave., San Jose, CA 95134; ph 408/894-3000, e-mail [email protected].