Challenges in the design and processing of future IC interconnects
03/01/2006
The 2005 International Technology Roadmap for Semiconductors (ITRS) predicts that up to 11 layers of hierarchical wiring with a cumulative wire length >1.4km will be used in microprocessor chips manufactured in 2007. Electron scattering within copper lines now significantly increases on-chip interconnect resistivity. Although copper and low-k dielectric materials will continue to be used, it is clear that desired system-level performance increases will require leveraging design and packaging technologies.
Robert Geffken, Geffken Associates, Burlington, Vermont
The prevalent interconnect theme for the last several years has been the integration of new materials to lessen parasitic delays in signal-propagation (proportional to the metal Resistance × the dielectric Capacitance, or the “RC” effect) due to scaled, reduced cross-section wires. Integration of new low-k dielectric materials to replace silicon oxide has been particularly troublesome, because the reduced mechanical properties of these materials limit compatibility with the chemical-mechanical planarization (CMP) needed in dual-damascene processing. Integration of porous low-k dielectrics with even less mechanical strength will be correspondingly more difficult.
Microprocessor (MPU) technologists are now more aggressively driving the metal pitch for MPU products. Traditionally, the most aggressive Metal 1 pitch was used by DRAM; however, the 2005 ITRS projects that the Metal 1 pitch for MPU will become equivalent to that of DRAM by 2010. In addition, the difference in pitch between the MPU Metal 1 and intermediate wires will disappear by 2009. Unfortunately, this accelerated pace of product shrinks will further exacerbate the performance and power issues associated with interconnect wiring.
Interconnect hierarchy
The ITRS predicts that up to 11 layers of wiring with a cumulative wire length >1.4km will be used on a 10mm square microprocessor introduced in 2007. A typical MPU cross-section is shown in Fig. 1. Tungsten studs in a planarized PSG pre-metal dielectric layer are typically used to make contact between the copper Metal 1 layer and the device gate and diffusions. A single damascene process is used for Metal 1, and the product layout uses staggered contacts to allow for the tightest pitch. A dual-damascene process is used for subsequent intermediate and global wiring layers. All Cu wires are encased by a metallic diffusion barrier on sidewall and bottom regions, and by a dielectric capping layer on top of the wire that also functions as a diffusion barrier.
 Figure 1. Cross-sectional schematic of a typical microprocessor that is expected to be manufactured in 2007, showing the hierarchy of the on-chip interconnect. |
This dielectric capping layer is the wire interface that now limits Cu electromigration performance. Improved conductive and dielectric barriers to replace this cap layer are being investigated and will be needed in the near future. The Metal 1 and intermediate wiring layers have the tightest pitch and therefore have the highest resistance per unit length; however, since they are typically used for local wiring, their lengths are short and the cumulative resistance is negligible. Moreover, the 70% shrink factor that generally characterizes new technology cycles means that the local wire lengths needed to contact transistors will also shrink, thereby reducing their resistance.
Fundamental performance problems occur in the global wiring levels, which contain wires that must traverse the entire IC chip. Microprocessor chip size has remained relatively constant through numerous technology cycles as manufacturers and consumers opted for higher performance and functionality rather than lower cost. Scaling of the global wiring levels must also occur in a technology shrink to efficiently interface with the tighter pitch Metal 1 and intermediate wires; however, these more resistive global wires would be a significant performance limiter. MPU designers have used a hierarchical wiring methodology, increasing pitch and thickness at each global conductor level, to alleviate this problem (Fig. 1). In essence, the initial global wiring levels are scaled and then connected to additional global wires, which are relatively unchanged in resistance and pitch from prior generations.
The worsening performance of global interconnect wiring over time is clearly shown in Fig. 2, where the relative delay of the transistor, local, and global wires is plotted versus process technology cycles. It is clear that scaling improves transistor delay and that local scaled wiring also shows an improvement; however, the delay in global wires gets significantly worse with successive technology cycles. The use of repeaters on global wires can alleviate the problem to some extent but the net result is still an overall increase in the relative delay. Increasingly, interconnect wiring has begun to both limit the performance of MPUs and also dominate the power dissipated during operation. One aspect of performance that is not reflected in Fig. 2 is the resistivity rise in Cu interconnects, which is seen as the width of wires approaches the electron mean free path in the metal.
The resistivity of a metal is a result of electron scattering from various sources. In the pure bulk metal, the scattering is primarily from thermal vibrations of the atoms in the lattice structure. The mean free path of an electron in Cu (i.e., the distance between scattering events) is about 40nm at room temperature. This lattice scattering component is primarily a function of temperature. However, as the width of lines starts to approach the mean free path of Cu, increased scattering events take place from sidewalls and other interfaces. In addition, grain sizes are also smaller for reduced-width damascene lines, and, therefore, scattering from Cu grain boundaries is also increased.
Measurements indicate that the observed increase in the resistivity of narrow Cu lines is almost equally due to two primary contributors: scattering from sidewalls and grain boundaries [1]. As seen in Fig. 3, their effect is significant for future technology cycles. For example, the effective resistivity of the Metal 1 line in an MPU will increase by slightly more than a factor of two for the 32nm technology cycle in 2013. This effect is being widely studied, but to date there do not seem to be any solutions that might significantly reduce the phenomenon.
Because of the nature of these size effects, the local wiring levels for MPUs will exhibit the highest effective resistivity for each technology node. However, since these wires are short in length and scale with technology shrinks, the effect of the higher resistivity on performance will be minimal. The same cannot be said for the global wiring levels where these Cu electron scattering effects will exacerbate the existing global interconnect problems. Existing models predict that these size effects will result in a doubling in the effective resistivity of a minimum pitch global wire by the year 2017.
This higher resistivity for Cu global wiring levels will have significant negative effects on performance and also result in increased power being dissipated in the interconnect structure. To track the impact of scaling and size effects on the performance problem associated with MPU global wiring, some key metrics have been developed and reported in the 2005 ITRS document. The RC delay, measured in picoseconds, for 1-mm-long minimum pitch global wires, both with and without electron scattering effects, through the year 2020 is shown in Fig. 4. It is evident that the effect of scaling has the most profound effect associated with minimum global wires, which will have an increase in delay of >20× by 2020. In addition, electron scattering effects will cause 2.5× more delay in the same timeframe.
 Figure 4. RC delay, measured in pico-seconds, for 1-mm-long minimum pitch global wires, both with and without electron scattering effects. |
Though delay is often considered as the primary metric of interconnect concern, crosstalk, noise, and power-distribution associated with decreasing geometries and increasing currents are also becoming a larger problem for both digital and analog circuits.
New interconnect architectures
Although Cu and low-k technology will continue to be pushed aggressively, it is clear that on-chip interconnect process innovations alone will not deliver the desired system-level performance and productivity improvements. Rather, leveraging other technology areas such as design and packaging should provide the greatest potential for near-term improvements. An interconnect-centric design methodology has been proposed to minimize critical paths and thus optimize performance. Unfortunately, since automated design tools for this approach do not currently exist, this is a very manpower-intensive activity.
Another potential solution is the Package Intermediate Interconnect concept, which proposes movement of some chip interconnects to the thicker metallization and higher performance wires on the package. An interposer chip, between the primary chip and the package, consisting only of interconnects, is another suggested packaging option. The Sea of Leads technology [2], which provides high density compliant I/Os on the chip, may be a key element to enable more seamless integration of the chip and package.
Since the global interconnect problem is essentially due to increased global wire lengths, some of the most exciting developments in the area of global interconnect performance improvement are three-dimensional integrated circuits (3DIC) [3]. 3DIC technology addresses the root cause of global interconnect delay by bringing the various IC components into closer proximity as multiple smaller chips in a vertical stack.
A number of different 3DIC options are currently being investigated. Chips can be bonded together face-to-face using various frontside bond pad configurations. Chips can also be stacked back-to-face using innovative through-holes in thinned wafers to make connections. Some 3DIC researchers also propose using active devices formed within the interconnect structure; however, the technical challenges associated with this implementation are certainly more formidable.
In recent years, there has been a great deal of debate about the relative merits of system-on-a-chip (SOC) versus system-in-a-package (SIP) concepts. It is clear that the larger die required for SOC would only worsen the global interconnect performance problem, as well as pose other issues of high process complexity and cost. Current SIP proposals seem to offer only limited performance advantages; however, it appears that 3DIC integration brings performance and density advantages, along with ease of integrating heterogeneous technologies.
References
- W. Steinhoegl, G. Schindler, M. Engelhardt, “Unraveling the Mysteries Behind Size Effects in Metallization Systems,” Semiconductor International, May 2005.
- B. Dang, C. Patel, H. Thacker, M. Bakir, K. Martin, J. Meindl, “Optimal Implementation of Sea of Leads (SoL) Compliant Interconnect Technology,” Proceedings of the IITC, 2004, pp 99-101.
- P. Joly, “Wafer Level 3D Integration,” Advanced Metallization Conference, 2004, pp 117-123.
Robert M Geffken, PhD, is co-chair of the ITRS Interconnect Technology Working Group and president of the interconnect technology consulting firm, Geffken Associates, 145 Crescent Beach Drive, Burlington, VT 05401; ph 802/658-3632, e-mail [email protected].