Technology News
02/01/2006
Chipmakers lean towards extending immersion lithography to 32nm
Seven of the nine major chipmakers interviewed by SST partner Nikkei Microdevices say immersion lithography currently looks like their most likely technology for 32nm production in 2009-2010. Only Intel and Matsushita Electric Industrial say EUV is their top candidate for 32nm.
Counting on EUV lithography means depending on suppliers to develop a common industry infrastructure. Its adoption would also mean everyone could print tiny features cleanly and easily with its short 13.5nm wavelength light, with no more need for optical proximity correction (OPC) or design for manufacturability (DFM) or the rest of the complex yield-enhancement tools chipmakers have developed. But extending immersion lithography, on the other hand, will take just the sort of complex OPC and DFM design skills that the major chipmakers rely on for their competitive advantage.
Lithography engineers at NEC Electronics and Renesas Technologies argue that many technical problems remain with EUV and that it won’t be ready in time for volume production by 2009-2010. Toshiba technologists say they hope to continue to use 193nm immersion for as many generations as possible.
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Still, EUV development continues to progress. Besides ASML’s widely reported plans to ship alpha tools to IMEC and Albany Nanotech by midyear, Canon intends to ship a small field exposure tool to Japan’s Tsukuba R&D Center by midyear, while Nikon will ship alpha tools to the Tsukuba R&D center and Intel by year’s end. Source suppliers EUVA, Xtreme, and Philips are reporting their tin discharge plasma sources are getting power at the intermediate focus up to 47W, 51W, and 46W, respectively, though the target level now may be closer to 180W, to allow for reducing resist sensitivity from 5mJ/cm2 to 10mJ/cm2 to solve line-edge roughness problems. Xtreme recently reported an 800W source that could get power at the intermediate focus up to around 80W.
Meanwhile, the industry is actually starting production with the first generation of immersion steppers, as makers of flash memory chips introduce the technology into volume fabs this year. Toshiba, which apparently has been using a Nikon tool in its development fab, is installing a Nikon S609-B in its Yokkaichi fab to start volume production of 55nm NAND flash in mid 2006. But the company has also reportedly purchased an ASML tool. Samsung is also evaluating both Nikon and ASML immersion steppers for manufacturing its 50nm flash in 2H06, but is expected to choose ASML to better mix and match with its ASML dry 193 tools.
 a) Nikon’s NSR-S609B immersion scanner. (Source: Nikon, Nikkei Microdevices) and b) ASML’s alpha EUV tool. (Source: ASML, Nikkei Microdevices) |
Of course, extending immersion to future nodes has plenty of problems, too, starting with high mask set costs, which are doubling every generation with all the complex corrections needed. And the higher NAs of immersion systems will mean even more complex requirements for masks, which are likely to push costs up even faster, as tighter geometries require even more sophisticated DFM. But for the regular patterns used in NAND flash, making two exposure passes can improve resolution considerably, though obviously at the expense of throughput. ASML has shown a k1 factor as low as ~0.2, making two exposure passes. With a 1.35 NA immersion stepper and water, it would print an hp29nm pattern. It exposes a mask once, then moves it over a half step and exposes it again, essentially cutting each line created in the underlying nitride hard mask into two. “Since this is limited to only the critical layers with the tightest pitch, the impact is minor,” says one Toshiba process engineer.
But immersion can’t be extended beyond the 32nm node without replacing both the water and the lens with new, higher index materials, which may be difficult. JSR, DuPont, and Mitsui Chemical have reported progress in developing high index fluids, but replacing the immersion liquid alone will probably improve resolution by only about 7%, so a new lens material will also have to be found.
The best high-index lens candidate looks to be some type of garnet. Yttrium aluminum garnet or YAG (Y3AL5O12) shows an index at 193nm of near 1.9; its intrinsic birefringence is lower by a factor of 2 than MgO at this wavelength; and the industry has experience processing it, making it an intriguing compound to start tinkering with. Substituting other materials for the yttrium improves the transmission, and Lu3AL5O12, with an index of 2.1, looks promising, according to the US National Institute of Standards and Technology. - SST partner Nikkei Microdevices
Research update from IEDM
At the December 2005 IEEE International Electron Device Meeting (IEDM), approximately 250 technical papers were presented to more than 1730 attendees, a record crowd for the Washington, DC conference location. The papers selected for the meeting, which represented just 35% of the total submitted, revealed major progress on a number of research fronts, including advanced MOS device techniques, low-k and high-k dielectrics, memory technology, and MEMS devices.
A paper presentation from the IBM, Sony, Toshiba, and AMD alliance on using enhanced transistor strain and an advanced low-k interconnect dielectric demonstrated impressive on-current performance of 735µA/µm for pFETS and 1259µA/µm for nFETS as well as an off current of 200nA/µm at the 65nm node. The researchers built a 0.65µm2 SRAM cell using the process, which implements all known methods of straining silicon: a dual stress liner using compressive stressed nitride on nMOS transistors and tensile stressed nitride on pMOS devices to provide optimum strain for each; embedded SiGe to place compressive strain in the source/drain regions of pMOS devices; and a stress-memorization technique that places a nitride layer on the gate before annealing, introduces strain during anneal recrystalization, and removes the nitride layer following the anneal to retain the strain. The technology uses an advanced low-k SiCOH-based dielectric with a k value of 2.75 to reduce interconnect delay by 6% in 10 wiring levels of wiring.
IBM also reported a novel process for creating a hybrid 100-110 crystal surface orientation on the same silicon wafer to take advantage of the fact that nFET devices operate faster on a 100 surface and pFETs operate faster on a 110 surface. Mixed-orientation substrates have been demonstrated previously in SOI technology, but not in standard bulk silicon. The paper described how the team built the mixed-surface Si substrate using a 65nm solid-phase epitaxy technique (see figure ). The result was a 35% performance improvement in nFET performance and a 20% reduction in ring oscillator benchmark gate delays.
 An electron microscope view of a cross-section of a direct- silicon-bonded substrate after solid-phase epitaxy (SPE) was performed in the selected area. (Courtesy: IBM) |
Advances in high-k included a novel process developed by Toshiba to deposit a 0.31nm thick layer of LaAlO3 dielectric, showing that work is continuing in lanthanum-based materials. By using a high-temperature (700°C) process to deposit an ultra-thin (EOT = 3Å) layer of La-aluminate directly on the Si substrate, the researchers showed that the dielectric reduced gate leakage to just 0.1A/cm2. The key to the laser sputtering-based deposition process was to form stable oxygen bonds in the film and suppress the formation of an interface layer such as SiO2 below the LaAlO3.
In the area of advanced memory, Sony has developed a new type of nonvolatile device called “Spin RAM” that could be the long-awaited universal memory in that it blends the high-speed, high-density, and low-power advantages of volatile memory with the data retention capabilities of nonvolatile memory. The technology takes advantage of the spin-torque of electrons and employs a memory cell that consists of a magnetic tunnel junction - two ferromagnetic layers separated by a spacer - and a transistor. The spin torque of the electrons flowing through the junction can be controlled to increase or decrease the resistance of one of the ferromagnetic layers. This change in cell resistance can be used to program the cell at low power without needing an external magnetic field, which could enable the technology to be highly scalable and a breakthrough for low-cost consumer applications. Using standard 180nm CMOS processes, the researchers built a 100 × 150nm 4kbit memory cell with 2nsec switching speeds at 300µA, which is 1/20th the power needed for a conventional MRAM.
In the MEMS arena, a team from the University of Michigan has designed a flexible electrode array with signal processing electronics to enable more accurate positioning of prosthetic implants into a hearing-impaired patient’s inner-ear cochlea than is possible with current implant technology. The paper describes how the system integrates a tiny thin-film substrate with a signal-processing chip to communicate with a microprocessor through a polymeric cable. Piezoresistive strain gauges measure the deflection of the array and a sensor tracks the contact made by the tip of the device with the cochlea wall. The device can then bend itself to better conform to the curved scala tympani and thus position itself deeper into the delicate ear structure to extend the range of pitch perceived by the patient. - P.L.
Progress toward metal gates, high-k
Several approaches to metal gate processing and integration with high-k dielectrics for the 45nm node and beyond were reported at the 2005 IEDM.
Most presentations focused on nickel silicide as the metal with one- or two-step processes to achieve fully silicided (FUSI) gates, and some showed how they could be combined with hafnium-based high-k gate dielectrics. Nickel was a natural choice because it is already fab-qualified and allows adjusting work function (WF) values up or down (depending on dopants). Analytical work on why the WF tuning works, suggesting how processing might be optimized, was also discussed. This approach avoids the complexity of using different metals for p- and n-channel devices with very short gate lengths.
Metal gates appear necessary as transistor scaling continues. The small charge-depletion layer in the traditional polysilicon gate adds to the effective thickness of the inversion layer over the p- or n-channel linking the source and drain. This was no problem with a thicker gate dielectric, but it does become a problem with gate insulators only four atoms deep. Depletion from the poly has climbed from 3% of the channel thickness in 1985 to about 50% in 2005. If metal is used for gates to eliminate the polysilicon depletion layer, it can enhance inversion charge density, but different WF metals will be needed in p- and n-channel FETs to get the WF at the band edge for high performance devices (perhaps 4.0-4.2eV for n-channel and 4.9-5.1eV for p-channel FETs). Processing is critical because the WF of integrated metal gates is dependent on deposition and annealing conditions.
Intel chose nickel silicide for metal gates because it is already in the process flow for 90nm and 65nm devices, so formation kinetics and processing steps are already known. It has a near mid-gap WF that can be modulated up or down by doping the poly-Si, and it has a low formation temperature (<400°C), according to P. Ranade et al.
A damascene “gate last” approach allows separate siliciding of the source-drain before the gate is exposed, so that the Ni thickness can be independently controlled. The FUSI devices showed a 20% improvement in inversion charge density over control devices due to the suppression of gate depletion. Experiments showed that phosphorous doping slightly lowered the WF while boron increased it. There was a 20% increase in drive current over the best achieved without the metal gate, Intel reported, and there was minimal impact on gate leakage, channel transport, and reliability. The authors believe that the WF shift is caused by dopants piling up at the gate junction with the oxide, but they declined to discuss specific results.
A cobalt silicide (CoSi2) barrier layer over active regions was added to NiSi FUSI gates in work reported by S. Yu, et al., Texas Instruments, to block nickel diffusion and prevent further silicidication of the silicon substrate. Two rapid thermal processing (RTP) steps are used, and no mobility degradation was found between the 35nm FUSI and poly-Si gate devices. They reported performance improvements of 15% for n-channel and 31% for p-channel devices.
A detailed study of WF engineering and scavenging for NiSi metal gates was presented by Y. H. Kim, et al., IBM. They suggested that high concentration ion implantation could have a snowplow effect, with dopant diffusion and delamination. In studying many materials, they found that adding aluminum and platinum to the NiSi improved high performance device characteristics when the metal gates interfaced with hafnium (Hf) compounds. The additives provided more stable diffusion compared to NiSi, perhaps by decreasing the number of Hf-Si bonds, while also allowing WF shifting. Experiments showed that NiAlSi and Ni-rich PtSi were the best candidates studied, but that too much aluminum may degrade mobility.
Another study of WF modulation at the Ni-FUSI/SiO(N) interface was reported by Yoshinori Tsuchiya et al., Toshiba. Many factors influence the work function, such as crystal orientation and material bulk properties as well as the silicide phase and the pre-doped impurity species, even under similar processing. The Ni/Si ratio significantly affects the bulk value of the WF. By separating the different effects, the authors found that the dominant effect is the pile-up of impurities at the interface between the silicide and the oxide. An effective WF model was developed based on the experiments. They suggest that the model explains not only the direction of WF shift, but also the range, indicating that precise control of impurity location is critical.
A novel single-step silicidization was described by M. Muller, Philips, along with co-authors from STMicroelectronics and CEA-LETI, Grenoble. To perform the junction and total gate silicidization in one step, the heights are adjusted with the initial Poly-Si gate 30-50nm higher, capped by a thick oxide hard mask and selective epitaxy on the S/D regions to raise the final silicizidation front. A two-step thermal treatment is used, with the second step at a higher temperature so the NiSi reacts with the remaining Si at the bottom of the gate. They called their devices totally silicided (TOSI), although the effect is similar to the FUSI work reported elsewhere. - B.H.
Tech Briefs
New interconnect topology for SoCs
STMicroelectronics has developed a new on-chip interconnect technology for system-on-chip designs, taking a page from its network-on-chip efforts. The company aims to improve the interconnection between IP blocks in the device, typically involving at least one processor core with dedicated IP blocks such as memories, audio/video codecs, and connectivity IPs, all connected by circuit-switched buses. ST’s new ST Network on Chip (STNoC), dubbed Spidergon, is an interconnection topology that arranges the IP blocks in a ring, with each connected to its neighbors as well as to other IP blocks, minimizing the number of nodes that a data packet travels in a routing algorithm. The company claims that this avoids the cost/performance tradeoffs faced by other topologies. - P.D., J.M.
Low-power phase-change memory cells
Hitachi Ltd. and Renesas Technology Corp. say they have successfully prototyped low-power phase-change memory cells that consume about 50% less power per cell than the companies’ previous technology, while generally matching other current nonvolatile memory properties. The cells use a film made by controlled oxygen doping of a germanium-antimony-tellurion (GeSbTe) material - which constrains the resistance of the film and suppresses the flow of excessively large currents during programming and can be changed from crystalline to amorphous phase with lower current and lower voltage. - J.M.