Trends and challenges in MOSFET scaling
02/01/2006
As in previous editions, the 2005 edition of the International Technology Roadmap for Semiconductors (ITRS) [1] projects rapid scaling of the physical dimensions for leading-edge MOSFET transistors, with values of the physical gate length (Lg) under 10nm beyond 2015. This scaling allows rapid improvement in the transistor performance, but new transistor structures and materials will be needed to meet key performance and leakage goals, which differ between high-performance and low-power ICs. Multiple paths in adopting and implementing these innovations are likely in the industry. This first article in Part 2 of our report on the 2005 ITRS (see p. 30 in January for Part 1) discusses the Process Integration, Devices, and Structures (PIDS) chapter of the ITRS.
Peter M. Zeitzoff, Sematech, Austin, Texas
The transistor scaling projections in the Process Integration, Devices, and Structures (PIDS) chapter of the 2005 ITRS were generated using MASTAR, a detailed MOSFET device simulation and modeling software package developed by ST Microelectronics that is well suited for efficient examination of tradeoffs [2, 3]. MASTAR deals with the key MOSFET physics for scaled devices, including short-channel effects (SCE), and has been validated against MOSFET data from the literature. In generating the ITRS MOSFET scaling projections, the following transistor parameters were among those varied iteratively until key device targets were satisfied: gate dielectric equivalent oxide thickness (EOT), physical gate length (Lg), work function of the gate electrode (φm), power supply voltage (Vdd), channel doping, etc.
The ITRS metric for the performance (speed) of the transistor is the nMOSFET intrinsic delay (τ) defined as
where C is the total gate capacitance per unit width (including fringing capacitance) of an nMOSFET transistor with gate length Lg, and Idsat is the saturation drive current per unit width. Note that, everything else being equal, to maximize the performance (i.e., to minimize τ), Idsat should be maximized.
The ITRS considers transistor scaling scenarios for both high-performance (HP) and low-power logic. HP logic is for high complexity applications such as MPU chips for desktop PCs and servers, while low-power logic is for mobile applications. For HP logic, the key MOSFET device target is high speed. This is achieved at the expense of relatively high leakage current because low threshold voltage (Vt) is required for high speed, since Idsat is directly dependent on (Vdd - Vt). Hence, the source/drain sub-threshold leakage current (Isd,leak) is high because it increases exponentially with decreasing Vt. The specific scaling target is a 17%/year decrease in τ, which matches the historic rate.
In contrast, for low-power logic, the key MOSFET device target is a low value of Isd,leak in order to maintain low static power dissipation, which is necessary to preserve battery life. The low Isd,leak requires high Vt, which results in relatively low speed. There are two flavors of low-power logic: low standby power (LSTP), which is typically for lower-performance consumer type applications such as cell phones, and low operating power (LOP), which is typically for relatively high-performance mobile applications such as notebook computers. For LSTP, lower-capacity batteries are typically used, while for LOP, large-capacity batteries are typically used. Hence, LSTP requires the lowest possible Isd,leak and correspondingly high Vt and low performance, while LOP can afford somewhat higher Isd,leak, which translates into higher performance.
For LOP, the dynamic power dissipation (also known as the “operating power”) must also be constrained. Since dynamic power dissipation is proportional to Vdd2, for LOP logic Vdd is scaled more rapidly than for LSTP and HP logic. Because of the impact of short channel effects, in order to meet the requirement of low leakage current, the Lg scaling for LSTP logic lags four years behind that of HP logic, while the Lg scaling for LOP logic lags two years behind. (The scaling of the other transistor dimensions for low-power logic lags correspondingly behind that of HP logic.)
 Figure 1. Key scaling results for high-performance (HP), low operating power (LOP), and low standby power (LSTP) logic transistors. (Source: 2005 ITRS) |
Figure 1 shows the overall results of the MOSFET scaling projection, which was done using the iterative approach discussed above. As expected, the performance and Isd,leak are highest for the HP transistors, medium for the LOP transistors, and lowest for the LSTP transistors. The rate of improvement of τ for HP logic is indeed at the targeted 17%/year, while Isd,leak is about four orders of magnitude lower for LSTP than for HP logic. The sharp reduction in Isd,leak between 2012 and 2013 for HP and LOP logic and between 2013 and 2014 for LSTP logic is associated with a shift from classical planar bulk to multiple-gate MOSFETs.
Static power dissipation, which equals leakage current × Vdd, is an important issue for HP logic. To keep the static power dissipation within tolerable limits, a common approach is to fabricate multiple transistors on the chip: the HP low-Vt transistors discussed above, as well as other transistors with higher Vt and higher EOT to reduce the leakage current. The HP transistors are used in critical paths, while the lower-leakage transistors are used everywhere else. As a result, the overall chip static power dissipation is notably reduced without significantly reducing the chip performance. Circuit and architectural static-power reduction techniques, such as utilization of pass gates to power down temporarily unused circuit elements or blocks, are also effective and commonly used.
MOSFET scaling challenges and potential solutions
For scaling as projected in the ITRS to take place, the industry must be capable of cost-effectively fabricating transistors with the required characteristics through the end of the Roadmap. The required characteristics include meeting the Isd,leak and transistor performance projections shown in Fig. 1, along with acceptable control of SCE, acceptable control of the statistical variability of the transistor parameters, acceptable reliability, etc. It turns out that there are numerous difficult challenges that arise as the technology is scaled with succeeding years, and that significant technological innovations (referred to as “potential solutions” in the ITRS) will need to be implemented in relatively rapid succession to deal with these challenges.
Mobility enhancement using strain. The first difficult challenge with scaling is increasing the Idsat as much as required while holding Isd,leak to acceptable values; this is particularly acute for HP logic. The preferred solution is to enhance the mobility beyond that attainable with standard silicon channels by using strained Si and possibly strained SiGe channels. Strained Si channels with enhanced mobility were implemented into products in 2004 [4]. Optimization of the strain is critical for effective enhancement of the mobility. Uniaxial strain along the channel direction has been reported as an effective technique for both nMOSFETs and pMOSFETs, with tensile strain being optimal for nMOSFETs and compressive strain for pMOSFETs. Strained silicon nitride layers on top of the transistor have been used to apply both tensile and compressive uniaxial strain [5], as well as SiGe layers selectively deposited in the pMOSFET source/drain to apply uniaxial compressive stress [6]. Mobility enhancement up to 1.8× that obtainable for unstrained Si channels has been reported for nMOSFETs, and even higher for pMOSFETs [7].
Gate leakage reduction using high-k dielectric. The gate leakage is due to direct tunneling of electrons through the gate dielectric, which increases sharply as the gate dielectric equivalent oxide thickness (EOT) is reduced. The ITRS specified maximum allowable gate leakage current density (Jg,limit) is closely related to the Isd,leak forecasts in Fig. 1. For HP logic, Fig. 2 shows the scaling of EOT, Jg,limit, and the simulated value of the gate leakage current density [Jg,sim(SiON)], assuming use of the current standard silicon oxynitride for the gate dielectric. The two Jg curves cross over each other in 2008, and hence for 2008 and beyond, oxynitride gate dielectric is incapable of meeting the maximum gate leakage current limit.
The potential solution being actively pursued by the industry is to use high-k gate material [8] (higher relative dielectric constant, k, than the 3.9 of silicon dioxide). As a result, for the same EOT, the physical thickness is larger for the high-k dielectric than for silicon dioxide (as well as for silicon oxynitride with k close to 3.9), so the direct tunneling and thus the gate leakage current should be lower for high-k dielectrics. For LOP and LSTP logic, a similar analysis indicates a need for high-k gate dielectrics in 2008. Note from the figure that, from 2005 through 2007, when it is assumed that silicon oxynitride is used for the gate dielectric, the scaling of EOT is quite flat to keep the gate leakage current within tolerable limits. However, EOT is sharply scaled down starting in 2008, when it is assumed that high-k will be available. Hafnium dioxide and hafnium silicate are the current leading candidates for implementation in 2008 [9].
Performance using metal gates. Another key challenge is electrical depletion in the polysilicon gate electrode when the transistor is turned “on” and an inversion layer forms. Polysilicon gate depletion increases the equivalent electrical oxide thickness, EOTelec, by 0.3-0.4nm, and hence reduces the value of Idsat that can be attained. As the EOT scales with succeeding years, the influence of polysilicon depletion on EOTelec becomes proportionately greater.
For HP and low power logic, the ITRS forecasts that by 2008, polysilicon depletion needs to be reduced below that attainable with polysilicon electrodes if the performance requirements on Idsat and τ are to be met. Metal gate electrodes, which have virtually no depletion, are being developed as the most likely potential solution [10-12]. To be able to set Vt to the appropriate value for pMOSFETs, the work function of the metal gate electrode must be near the silicon valence band (similar to p+ doped polysilicon electrodes). For nMOSFETs, the work function must be near the silicon conduction band (similar to n+ polysilicon electrodes). It is likely that different metals with appropriate work function for the pMOSFET and the nMOSFET, respectively, will be used (i.e., the “dual-metal gate” electrode solution).
Advanced device structures. Even with use of the above technology innovations, effective scaling of classical planar bulk MOSFETs is expected to become increasingly challenging for 2008 and beyond, when Lg for HP logic transistors is forecast to be ~20nm and below. Achieving adequate control of SCE for such small devices will be especially difficult. Exceedingly high values of channel doping will be needed to control these effects, and this high doping will lead both to reduced mobility and increased band-to-band tunneling leakage current. Furthermore, the total number of dopant atoms in the channel for such small MOSFETs is relatively small, which leads to large and irreducible statistical variation in the number and placement of the atoms, and hence to unacceptable statistical variation in Vt. A potential solution is the use of ultra-thin-body fully depleted silicon-on-insulator (UTB FDSOI) single-gate MOSFETs (Fig. 3). These have lightly doped channels, and Vt is set by the work function of the (metal) gate electrode not by dopant atoms in the channel, so the variation in the number of dopant atoms does not affect Vt. Scalability and control of SCE are significantly enhanced, although reliably controlling the thickness will presumably be a major challenge.
Multiple-gate MOSFETs, which also have ultra-thin, fully depleted bodies (Fig. 3), are likely to be used eventually. Such devices typically have a narrow silicon fin with the gate electrode wrapped around two or more of the fin edges (the term “FinFET” is often used for the double-gate version), and the current flows along these edges. They are often, although not always, fabricated on SOI substrates, as shown in the figure. The scalability of the multiple-gate MOSFET is improved beyond that of the single-gate UTB FDSOI MOSFET [13-15], mainly due to the shielding effect of the wrap-around gate electrode. Both single-gate SOI and multiple-gate MOSFETs require the gate’s work function to be in the vicinity of the silicon midgap so that Vt can be set to the desired value. Since it is impractical to use polysilicon with such work functions, metal gate electrodes are required.
The timing of the potential solutions in the PIDS chapter is based on the scaling scenario discussed above, and it reflects when each potential solution is needed to meet key transistor performance and leakage targets. This timing is aggressive, with numerous major technology innovations required over the next few years. This is particularly so in 2008, when high-k gate dielectric, metal gate electrodes, and single-gate UTB FDSOI are all forecasted; it will be very challenging for the industry to implement all these major innovations in the same year.
A major change in the 2005 PIDS chapter is that multiple parallel paths are followed for MOSFET scaling, with significant overlap among planar bulk CMOS, single-gate UTB FDSOI, and multiple-gate timings. HP logic, LOP, and LSTP logic follow similar multiple paths. The multiple parallel paths were chosen because they reflect the most likely scenario for the industry, since some companies will likely scale planar bulk CMOS as long as possible, while others may make an early switch to FDSOI or multiple-gate MOSFETs. The PIDS chapter projects multiple-gate MOSFETs for implementation in 2011; because of its superior scalability, the multiple-gate MOSFET is projected to be the ultimate MOSFET toward the end of the Roadmap.
References
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Peter M. Zeitzoff is chair of the ITRS Process, Integration, Devices, and Structures (PIDS) International Technology Working Group (ITWG) and is a Senior Fellow at Sematech, 2706 Montopolis Drive, Austin, TX 78741; e-mail [email protected].