Frontend processes required for continued CMOS scaling
02/01/2006
During the next several years, frontend processes will require the introduction of a variety of high-k materials and highly-engineered metal films for applications as diverse as MOSFET gate stacks, DRAM storage capacitors, and flash-memory storage devices. In addition to these new materials, new device structures, such as fully depleted silicon-on-insulator (FDSOI) and FinFETs (including dual- and multigate), will be introduced to meet performance requirements. Alternative memories will require the development and optimization of a broad class of ferroelectric, magnetic, and phase-change thin film materials. Substrate requirements are rapidly evolving, including the need for larger, 450mm-diameter, silicon substrates within the next seven years.
J. Butterbaugh, FSI International, Chaska, Minnesota
C.M. Osburn, NC State University, Raleigh, North Carolina
The Front End Processes (FEP) chapter of the 2005 ITRS attempts to identify the challenges and potential solutions to “materials-limited device scaling.” The transition from extended bulk CMOS to nonclassical device structures is not expected to take place at the same time for all applications and all chip manufacturers. Instead, a scenario is envisioned in which a greater diversity of technologies are used competitively at the same point, with some manufacturers choosing to make the transition to nonclassical devices earlier, while others emphasize extensions of bulk technology. To support this probable scenario, the FEP International Technology Working Group (ITWG) has provided metrics for parallel paths showing what is required to extend classical CMOS and what can be gained by making a transition to other structures such as FDSOI and multigate devices (Fig. 1).
 Figure 1. Parallel paths for advanced device design to meet performance requirements. |
The FEP tables have been lengthened to accommodate entries for extended bulk, FDSOI, and multigate structures during the years when those technologies are expected to overlap. The requirements for these parallel paths are intended to illustrate some of the trade-offs associated with each alternative technology. For example, bulk CMOS extensions will require more aggressive scaling of gate dielectric thickness and junction depth, while requiring lower resistance contacts. On the other hand, FDSOI and multigate devices need gate electrode materials whose work functions are different than those used in bulk CMOS.
Silicon wafer trends, addressed in the FEP Starting Materials section, include several changes that deal with scaling, yield enhancement, and productivity improvements. Edge exclusion has been reduced from 2 to 1.5mm at the 65nm technology cycle for consistency with the Factory Integration ITWG’s direction. Reduced edge-exclusion generally poses broad challenges for all FEP sub-ITWGs, including the starting wafer; it is particularly difficult for SOI wafers where the thin silicon layer does not extend all the way to the substrate edge, leading to the creation of a separate edge-exclusion table entry in the SOI section. In the nearer-term, silicon thickness values for FDSOI structures were scaled downward to be consistent with the latest ITRS Process Integration, Devices, and Structures (PIDS) requirements. Long-term manufacturing and controlling the thickness of FDSOI layers have no known solutions and, as a result of further scaling, face even greater challenges.
The need to reduce front-surface particles and their size has accelerated, with 65nm particles now important at the 50nm technology cycle and 45nm particles becoming a concern at the 32nm cycle. The wafer diameter title in the tables was changed to the maximum substrate diameter to match the terminology used in the overall Roadmap technology characteristics (ORTC) lithographic-field and wafer-size trends tables. This also appears to more accurately reflect the existence of multiple wafer diameters that indeed are used for device production at a given technology cycle. Finally, an extensive discussion of emerging materials trends and opportunities is presented in the Starting Materials section of the FEP chapter via a hyperlink, and has also been published in the January 2006 issue of SST [1].
With the advent of new materials and integration schemes, surface-preparation at the 90nm cycle and beyond is far more challenging than just cleaning the wafer. The formation of the gate dielectric and electrode demand the tightest control of parameters associated with critical cleaning. The ability to remove particles smaller than one-half the DRAM M1 half-pitch without damaging the wafer is a formidable challenge. Maintaining high cleaning efficiency while removing less than 0.4Å of material and without damage to 23nm wide gate structures will present a major challenge as early as 2008. Concurrently, metallic contamination must be reduced to, or maintained at, levels that do not affect device performance.
Other critical surface-preparation areas are removing high-dose implanted photoresist, cleaning and drying high aspect ratio features such as contacts and capacitor structures, and cleaning fine features such as polysilicon lines without damage. To address these challenges, new cleaning techniques, equipment, and chemicals are required. In addition, the influence of back-surface particles on yield and the need for their removal continue to receive a lot of attention. New back-surface defect metrology tools should bring a better understanding of this area in the next few years.
Transistor gate formation
Scaling the equivalent oxide thickness (EOT) of the gate dielectric remains a key FEP challenge. However, the need for high-k dielectrics was moved out one year, to 2008, from the last edition of the ITRS, thanks to a combination of more aggressive scaling of junction depths and the use of strain to enhance channel mobility. Figure 2 indicates the need for high-k when the gate leakage current of oxynitride is projected to exceed the leakage requirement. The 2005 Roadmap also brings an increased realization that in the longer-term, gate dielectric leakage needs to be capped at lower values than previously anticipated. In the short-term, approaches to minimize poly-Si depletion become increasingly important.
The methodology used for defining and displaying the EOT of the gate dielectric changed in 2005 to better reflect the effect of gate depletion. In both the 2003 and 2005 editions of the ITRS, the gate stack (dielectric plus electrode) requirements originated from the electrical equivalent thickness in the PIDS device designs. The capacitance (electrical) equivalent thickness (CET) includes not only the EOT but also gate depletion and the effect of quantization in the channel. These latter two effects were more accurately calculated for the 2005 Roadmap, and EOT requirements were tabulated for light, nominal, and aggressive poly-Si gate doping levels (1.0, 1.5, and 3.0 × 1020/cm3, respectively) as well as for metal gates having no depletion.
Series resistance of contacts and junctions takes on increased importance in the 2005 ITRS for several reasons. Shallower junctions are forecasted in the short term to help delay the need for high-k gate dielectrics. Intermediate-term, bulk CMOS extensions require very aggressive scaling to control short-channel effects. FD SOI devices and FinFETs require selective deposition of elevated junctions to even be able to make contacts. As a consequence, there are no good solutions to the series resistance challenge over large portions of the Roadmap.
Control of the physical gate length continues to be a difficult challenge for FEP and lithography. A survey revealed that manufacturers were almost universally unable to control the CD to within 10% (3σ), as prescribed in the 2003 ITRS. Pathways around this potential barrier were found by continuous discussions between the FEP, PIDS, Lithography, and Design groups. As a result of this collaboration, changes were made across several chapters of the ITRS based on the recognition that devices can be economically manufactured with slightly higher variation than previously prescribed. Accordingly, the CD tolerance increased to 12% (3σ) in 2005; and analysis is ongoing to see if the tolerance can be further relaxed, e.g., to 15% in the future.
Although the final MPU physical gate lengths remain unchanged from the values in the 2003 ITRS, the printed dimensions were made larger while the amount of resist trimmed away was increased. Along with this change, the partitioning of the total CD tolerance components was changed to 75% lithography and 25% etch, from the 80%/20% split in the 2003 ITRS (Fig. 3). At the same time, evidence is growing that the industry is actually using slightly larger physical gate lengths than those in the ITRS. The evidence is not yet strong enough to warrant a change in the numbers in 2005, but if a trend is discerned, the physical gate length values may be revised upwards at the next revision.
Memory structures
For DRAM stacked capacitors, metal-insulator-metal (MIM) structures with high-k dielectrics are now required to meet capacitance requirements. Beyond 50nm (2009), a new dielectric material with a dielectric constant >60 will be required. Embedded DRAM in SOC applications will drive several integration challenges. One of those challenges is matching the ground rules required for the deep contacts around the stacked capacitor with the contact ground rules for the logic device. The need for advanced capacitor materials in the DRAM trench capacitor are delayed relative to the stacked capacitor by only a few years. Some high-k materials are currently being used in a silicon-insulator-silicon (SIS) structure for trench capacitors, but a metal-top electrode will be needed by 2007 and a full MIM structure with high-k dielectric may be needed by 2009. The cell size factor for the DRAM stacked capacitor is 6, while that for the DRAM trench capacitor remains at 8.
The rapid expansion of the market for flash memories brings more focus on the material and process challenges for these devices. With this acceleration, flash memory is becoming a new technology driver for both critical dimension scaling and material technology. The effective dimension, F, of Flash NAND devices now appears to lead the DRAM half-pitch in scaling. As the space between adjacent poly-Si gates shrinks, however, it will no longer be feasible for the control gate poly-Si to overlap the sides of the floating gate. Thus, by 2010 high-k interlayer dielectrics will be required to maintain an acceptable capacitance coupling ratio. In that same year, ferroelectric RAMs (FeRAMs) are projected to need 3D capacitors to provide charge storage that is competitive with DRAM (~30µC/cm2).
450mm silicon wafers
The introduction of 450mm wafers in the FEP Starting Materials tables has been pulled in from 2015 and now appears in 2012, consistent with the direction from the ORTC. Motivation for the newly indicated timing is driven chiefly by productivity enhancements suitable for keeping pace with Moore’s Law. On the other hand, productivity alternatives related to design, such as multivalued logic or innovative architecture, may be pursued by many others.
Migration to the next diameter wafer has historically occurred roughly on a 9-11 year cycle, so the industry is already several years behind schedule for a 2012 introduction. Furthermore, a number of highly coordinated actions such as setting standards must occur before any silicon wafers or processing equipment development can start. In contrast to the 300mm transition, which mainly focused on economic issues, the transition to 450mm faces both enormous technical challenges and economic risk.
One key starting issue is whether 450mm wafers will be SOI or bulk, since the proposed timing of 450mm is likely to correspond with a broader adoption of SOI within mainstream IC production, particularly for high-performance logic/MPU applications. Certainly the wafer type (polished, epi, annealed, or SOI) drives standards, metrology, and processing. While unparalleled progress was made in the standardization of 300mm wafers, 450mm will call for an even more efficient approach, particularly to reduce the time required from initiation to completion of standards, to avoid costly and time-consuming iterations.
Specific attention must be paid to materials strength considerations of the silicon wafer, during both wafer production and device processing, calling for a more careful determination of the wafer thickness standards. Indeed, there already are indications that some IDMs are using thinner than standard 300mm starting wafers to reduce the amount of backside grinding needed to ensure that ICs fit into advanced packages.
Concurrent with the development of global standards, suppliers across the entire spectrum of materials and equipment must also address the technical challenges associated with wafer, metrology, and processing equipment development. With sufficient resources and collaborative planning between the IDMs and the supplier community, the technical challenges may be overcome in time, but in a manner not necessarily on par with past cost models.
The economic challenges of 450mm are arguably more daunting than the myriad technical ones. The cost of migration from 300mm to 450mm is estimated to be several tens of billions dollars, at a minimum. Device, materials, and processing companies will all need to allocate significant resources to this end. Given the magnitude of these costs, it is likely that many IDMs will not be capable of affording 450mm alone, leading to an increased number of consortia, joint manufacturing ventures, and contract manufacturing. It will essentially mandate that IDMs provide significant financial backing to material and equipment suppliers to partially defray those costs and obtain a reasonable ROI for such suppliers; it may even necessitate government funding. In any case, one might consider that the extensive support required for the 450mm conversion may take away required support for the continued improvement of 300mm wafers, of special concern for those IDMs not desiring to participate in 450mm conversion, either initially or at all. Perhaps the foremost prerequisite before embarking on a 450mm development program is a broad industrial coalition that includes agreement on funding sources and transition timing.
Acknowledgments
More than 100 people contributed to the Front End Process Chapter. Of this total, 32% came from chipmakers, 47% from equipment manufacturers and suppliers, and 21% from universities, research institutes, or consulting firms. Of particular note were the International Technical Working Group Members (M. Alessandri, M. Gutsche, M. Kubota, I. Mizushima, W. Mueller, T. Nakanishi, and J.-S. Roh) and the domestic Sub-TWG chairs (J. Barnett, H. Gossmann, H. Huff, M. Ieong, L. Larson, S. Lohokare, K. Reinhardt, G. Smith and M. Walden).
Reference
- M. Bulsara, G. Celler, T. White, B.W. Standley, H.R. Huff, “Emerging Electronic Materials for Future CMOS Applications,” Solid State Technology, p. 34, January 2006
Jeff Butterbaugh is the co-chair of the ITRS Frontend Processing ITWG and chief technologist at FSI International, 3455 Lyman Blvd., Chaska, MN 55318; e-mail [email protected].
Carl Osborn is the co-chair of the ITRS Frontend Processing ITWG and professor of electrical & computer engineering at North Carolina State U., Raleigh, NC.