Many options expected in the future of lithography
02/01/2006
The 2005 ITRS details the qualitative challenges associated with - and the quantitative requirements for - lithography using the incumbent projection imaging at 193nm wavelength with immersion lenses. The possible future alternatives are forecasted to be EUV, maskless, and/or nanoimprint lithographies. Along with the technical challenges, the economic challenges of developing one or more lithography technologies that meet all of the technical requirements are highlighted.
Scott Hector, Freescale Semiconductor Inc., Austin, Texas
Maintaining the historical pace of reducing half-pitch for each technology generation requires overcoming the challenge of extending the incumbent optical projection lithography technology at 193nm while simultaneously developing alternative, next generation lithography (NGL) technologies. Not only is it necessary to invent technical solutions to challenging problems, it is critical that die costs remain economical even as the costs of design, process development, masks, resist, and exposure tools rise. Maintaining economical production costs is becoming a bigger challenge as the rising costs of developing a new generation of lithography technology must be amortized over relatively few generations of integrated circuits.
In the Difficult Challenges tables in the 2005 ITRS, stronger emphasis was placed on challenges related to immersion lithography. The 2005 chapter includes more detail describing cost of ownership, resolution enhancement techniques (RET), and design for manufacturing (DFM) with lithography-friendly design rules.
Continued emphasis was placed on challenges for implementing cost-effective post-optical lithography solutions, and more detail was added on the requirements for extreme ultraviolet (EUV), imprint, and maskless lithographies.
Lithographic technologies
Since the 2003 International Technology Roadmap for Semiconductors was published, the Lithography International Technology Working Group (ITWG) members have defined new criteria for evaluating near-term potential solutions for lithography. Solutions shown in Fig. 1 for the present and succeeding technology generations must address leading-edge requirements in at least two geographic regions, and all infrastructure including resist and mask must be ready for the timing of the technology generations.
Solutions for three generations or more in the future include more risky options to encourage continued innovation. Within these criteria, 193nm wavelength exposure systems, including 193nm immersion systems, became dominant solutions for the next two technology generations. Furthermore, immersion lithography appears as a potential solution at the 32nm and 22nm cycles if high index fluids and lens materials are developed to extend the use of immersion beyond the limits of water-based immersion. The use of two masks per exposure field - with each mask having patterns with half-pitch two times larger than the primary half-pitch - might also help extend immersion lithography.
EUV lithography is the most probable potential solution for 32nm and 22nm half-pitch. Imprint and maskless lithography are other options along with innovative immersion. A table describing the requirements for imprint templates was added. No longer are the use of 157nm wavelength and electron beams in combination with masks (e.g., electron projection lithography or proximity electron lithography) anticipated as potential solutions.
Patterning requirements
Significant changes were made to overlay and CD control tolerances in the 2005 update. The table includes a subset of the quantitative, high-level requirements for pattern formation, optical masks, and resists described in several tables of the update. Overlay tolerances have decreased by about 40% since the 2003 Roadmap to reflect requirements for memory circuits to be fabricated with higher yield. To reduce the effect of lens distortion on overlay error, a single exposure tool may be used to print multiple critical layers for the same wafers.
 |
In addition to updating overlay requirements, the Lithography ITWG has participated in discussions with working groups developing other chapters to define CD control requirements. The working groups in the US and Japan separately conducted simulation studies that concluded that <4nm 3σ CD control has no known solutions with any technology presently being developed. Because of the particular challenges associated with imaging contact holes, the size of contact holes after etch will be smaller than the lithographically imaged hole, similar to the difference between imaged and final MPU gate length.
High frequency linewidth roughness affects dopant concentration profiles and interconnect wire resistance. Linewidth roughness at larger spatial frequency results in variations of transistor gate length over the active region of the device. This variation increases leakage of transistors and causes a variation of the speed of individual transistors, which in turn leads to IC timing issues. The definition of linewidth roughness has been refined and values of low frequency roughness have been established with the intent to establish high frequency values in the future. Metrology tools need to be modified to accurately measure these critical variations.
Masks
The extension of optical projection lithography to patterning features with a half-pitch ≤65nm places significant demands on the mask. The 2005 ITRS continues to focus on the evolving requirements for mask fabrication and use. Figure 2 provides an overview of masks required for 193nm, EUV, and nanoimprint lithography.
For 193nm lithography with immersion lenses, strong RET is required to compensate for diffraction and limited depth of focus (DOF). Extensive use of subresolution assist features (SRAF), embedded phase shift masks (PSM), complex model-based optical proximity correction (OPC), and increasing application of alternating-PSM is likely. Critical dimension errors on the mask might be magnified [i.e., mask error enhancement factor (MEEF) >1] in the optical projection lithography process, which is being pushed near its resolution limits. SRAFs might be 50% smaller than primary features. The requirements for SRAF size, mask minimum primary feature size, mask CD uniformity, mask pattern placement, defect size, linearity, and CD mean-to-target control do not have manufacturable solutions for ≤45nm half-pitch patterning.
EUV masks are similar to optical lithography masks, but they are used in reflection rather than transmission. For both types of masks, a patterned absorber layer contains the information on the mask. For EUV masks, a multilayer stack comprising alternating layers of Mo and Si acts as a distributed Bragg reflector and makes up the mask blank. The absorber stack has an absorbing layer or layers; it is separated from the multilayer reflector by a buffer layer and optional capping layer. Fabricating a low-cost EUV mask blank is the greatest challenge for EUV masks [1]. Many of the challenges of patterning are common to any lithography technology used for <45nm half-pitch patterning, for example, the substrate and multilayer stack must be free of printable defects.
While optical and EUV mask features are 4× printed feature sizes, nanoimprint templates require 1× patterns, so enhanced pattern generators and repair tools, plus new techniques for template inspection and defect review must be developed. However, the challenge of making templates relative to the challenge of making optical projection masks is partially mitigated because the templates do not have the subresolution assist features required for optical masks. Furthermore, the area of the pattern to be written, inspected, and made defect-free is 16× smaller than for 4× optical or EUV masks [2].
Acknowledgments
The author would like to thank the US Lithography TWG co-chair, Maureen Hanratty, as well as the chairpersons of the lithography TWGs from Taiwan, Korea, Japan, and Europe for many fruitful discussions that led to this update of the lithography chapter of the 2005 ITRS.
References
- Scott D. Hector, Kevin Kemp, “EUVL Mask Challenges and How International Sematech is Addressing Them,” Symposium on Photomask and NGL Mask Technology XI, SPIE Proceedings Vol. 5446, ed. Hiroyoshi Tanabe, 792-803, August 2004.
- William M. Tong, Scott D. Hector, Gun-Young Jung, Wei Wu, James Ellenson, et al., “Nano-imprint Lithography: The Path Toward High Tech, Low Cost Devices,” to be published in Emerging Lithographic Technologies IX, Proceedings of SPIE, ed. R. Scott Mackay, 46-55, May 2005.
Scott Hector has been chairman of the ITRS US Lithography International Technology Working Group since 2004 and is the manager of DFM methodology at Freescale Semiconductor Inc., 7700 West Parmer Lane, MD PL29, Austin, TX 78729; e-mail [email protected].