Technology News
01/01/2006
Quantum transport phenomena could lead to new applications in carbon-based electronics
Two papers in the November 10 issue of Nature report remarkable observations in the electronics of graphene - a carbon macromolecule with the structure of chicken wire that when stacked is called graphite. Researchers have learned how to pull individual molecules off the surface of Kish graphite from Toshiba Ceramics and to measure the electrical conductivity. Since carbon has four valence electrons, but only three are needed for bonds, one per atom is free to wander through the two-dimensional graphene lattice.
However, graphene is very different from more familiar 2D quantum wells in semiconductors. The low-energy band structure, for example, consists of cones at the corners of the Brillouin zone, rather than paraboloids at the center. The tips of the (normally empty) conduction band cones touch the tips of the (normally filled) valence cones at “Dirac points” where the density of states vanishes. The net effect, according to researchers at Columbia U. (Y. Zhang, Y-W. Tan, H. L. Stormer, P. Kim), is that the electrons and holes in graphene behave like the electrons and positrons described by Dirac’s relativistic wave equation, except with zero rest mass and the Fermi velocity (~106m/sec) substituting for the speed of light. The resulting variety of exotic solid-state phenomena could possibly lead to new applications for carbon-based electric and magnetic field-effect devices. Potential uses cited by the researchers include ballistic metallic/semiconducting graphene ribbon nanoelectronics and electric field-sensitive spin transport (spintronic) devices.
The electric field dependence results from the sensitivity of graphene conductivity to the voltage on a nearby gate electrode. In the experiments reported, a conductive substrate (a degenerate silicon wafer coated with 300nm of SiO2) acted as the gate. The field emanating from the gate changes the doping of the graphene, producing free electrons or holes in the conical bands (depending on the sign), or enforcing charge neutrality. At low temperature, charge neutrality implies both the absence of free carriers and the low-lying states for them to inhabit, which should result in an infinite resistivity. K. Novoselov at the U. of Manchester and collaborators, however, found a well-defined maximum resistivity near h/4e2, one-quarter of the single-channel resistivity quantum. At higher carrier density (higher absolute gate voltage), the conductivity varied linearly with carrier concentration for both holes and electrons.
In a perpendicular magnetic field, the Lorentz force creates a sideways motion of the carriers and a sideways current described by the “Hall conductivity.” The reversal of the sign of the Hall conductivity at charge neutrality showed that both holes and electrons could appear. Graphene also showed other bizarre quantum behavior: When there is sufficient magnetic field, charge carriers can be expected to move in circular cyclotron orbits, quantized into Landau levels. The ordinary and Hall conductivity depend on the filling of those quantum levels, resulting in the quantum Hall effect, for which Nobel Prizes were awarded in 1985 and 1998. The unusual band structure of graphene results in an extra “pseudospin” degree of freedom absent in other cases (and also absent for the lowest Landau level in graphene). The result is that the quantum Hall effect in graphene shows conductivity plateaus at half integral values of 4e2/h (±1/2, ±3/2, etc.) rather than at integral values or fractions with an odd denominator, the cases for which Nobel prizes have already been awarded. That odd behavior was absent in samples composed of even two graphene sheets.
Graphene appears to present solid-state analogs for many of the most mysterious predictions of Dirac’s relativistic wave equation, and one can expect to see numerous future studies of this unique material. Applications of the high mobility and unique band structure may have to wait for improvements in nanotechnology. Still, it is clear that, even in 2005, familiar materials like graphite reveal surprises when studied at the nano level. - M.D.L. and D.V.
Nanocrystalline silicon may cut flash memory costs
Freescale Semiconductor says replacing floating polysilicon gates with nanocrystalline silicon will cut chip size and mask steps, significantly reducing the cost of its embedded flash memory products, starting with the 65nm node in 2008-2009.
The company has demonstrated a 24Mbit memory array made with 90nm process technology, using gates made of a monolayer of nanocrystals of silicon, encapsulated in a dielectric oxide. The process achieves the necessary bit-to-bit uniformity primarily by basic process control with conventional deposition tools, making ~50Å crystals arrayed at a density of ~1012/cm2. “We can find the conditions and temperatures that allow us to control the size and density pretty well,” says Bruce White, Freescale’s manager of advanced materials, memory, and interconnect.
 Replacing floating polysilicon gates with nanocrystalline silicon will cut chip size and mask steps. |
Embedded flash is facing scaling limits, as the 9-12V high-voltage transistors typically required to reliably write and erase the charge on conventional polysilicon gates take up an excess of valuable chip real estate, and the gates need to be encased in thick dielectrics to maintain their charge for years.
Breaking up the floating gate into lots of little separate zones means a defect in the dielectric will affect only one separate bit, and not lead to a complete loss of charge in the whole gate, so the encasing dielectric can be made significantly thinner. And operating voltage can be reduced to around 6V, allowing memory array size to be reduced by about 50% at 90nm. “The lower voltage also means we can commonize a lot of the processes with logic,” says White. “So we can reduce [the related processes] from 10-11 masks down to four.” The issue now in integrating the process is to keep the crystals from oxidizing. He says the nanocrystalline silicon thin-film approach is one of the few candidates for next-generation flash technology that has demonstrated the reliability needed for the automotive applications of Freescale’s embedded memory.
Though Freescale is focused only on embedded applications, the technology could potentially be used in other flash memories as well, as the very fine pitches at next-generation geometries mean the capacitance coupling between the floating gate and the control gate and thus the bit content is likely to be disturbed by surrounding features. “The nanocrystalline structure is fairly immune to interference,” says Freescale manager of memory devices Ko-Min Chang. “It also has the opportunity to extend the stand-alone roadmap, if anyone is interested.”
The company is using standard polysilicon floating gates for its 90nm-generation embedded flash, so the new approach is targeted at 65nm. Researchers will next focus on figuring out the right specifications for the size of the crystals, the best encapsulating materials, the bottom oxide thickness, and other items. - P.D.
Sequential UV annealing of dielectrics
A new ultraviolet thermal processing platform from Novellus blends industry-standard lamp-based UV light sources with the company’s multistation sequential processing architecture. With transistor and interconnect fabrication applications that require 5-10 min of total annealing, the SOLA (sequentially optimized luminescent anneal) tool should deliver 20-40 wafers/hr proportional throughputs.
Based on the Vector platform, the 300mm tool features four stations through which each wafer passes in series (see photo). Multistation single-wafer processing in this manner averages nonuniformities within each station for improved within-wafer uniformity. Each station allows for different temperatures, light frequencies, and lumen intensities to be set, so multistep anneals can be performed even though the time at each station remains constant.
 The inside chamber of the SOLA tool, which uses a more efficient design for higher throughput and improved process control. |
Multistep anneals will probably be essential for forming porous low-k films, with separate steps likely to be needed for porogen outgassing, and molecular cross-linking to enhance mechanical rigidity. Results from a 1000-wafer marathon run using SOLA to form and strengthen a porous-SiOC layer showed 0.9% (1σ) within-wafer nonuniformity, though throughput remains to be determined.
Porogen outgassing results in polymer vapors floating through the annealing chamber, which deposit on chamber surfaces including the UV lamp windows. To maintain controlled lumen intensity during annealing, the windows must be periodically cleaned.
Special purge hardware, some manner of an inert-gas “curtain,” allows >100 porous low-k wafers to be processed between cleans using either O3 or remote plasma. To avoid lost annealing time, intensity monitors behind the windows determine when cleans are actually necessary. - E.K.
News Briefs
Silicon’s building block synthesized - The smallest discretely defined repeat unit that can be plucked from the silicon crystal lattice has been synthesized as an independent molecule by a team of Austrian chemists, as reported in Science 2005, 310, 825. “Sila-adamantane” is a tricyclic Si10 cluster with pendant methyl and trimethylsilyl groups. The molecule is anticipated to help scientists better understand how the properties of silicon transition from the molecular level to the bulk solid. Sila-adamantane was synthesized by Jelena Fischer, Judith Baumgartner, and Christoph Marschner of Graz U. of Technology. Marschner says that sila-adamantane’s structure should impart properties that could make it suitable for use in molecular electronics, such as constructing molecular wires and miniaturized semiconductor devices.
Study of cadmium selenide nanostructure growth yields production roadmap - Researchers have taken an important step toward high-volume production of new nanometer-scale structures with the first systematic study of growth conditions that affect production of one-dimensional nanostructures from the optoelectronic material cadmium selenide. Using the results from more than 150 different experiments in which temperature and pressure conditions were systematically varied, nanotechnology researchers at the Georgia Institute of Technology created a “roadmap” to guide future nanomanufacturing using the vapor-liquid-solid technique. The results, reported in the journal Advanced Materials, provide a foundation for large-scale, controlled synthesis of nanostructures for future sensors, displays, and other nanoelectronic devices.
IBM researchers slow down light on a chip - Reported in the November 3 issue of Nature, Yurii Vlasov and co-workers at IBM’s T.J. Watson Research Center have applied photonic crystal technology to ‘slow light’ on a chip. In their work, pulses of light are drastically slowed and even brought to a halt in various atomic and solid-state systems via an ultracompact photonic IC using low-loss silicon photonic crystal waveguides that can support an optical mode with a submicron cross-section. The researchers demonstrated a 300-fold reduction of the light group velocity on a silicon chip. In addition, the researchers showed fast (100 nsec) and efficient (2mW electric power) active control of the group velocity by localized heating of the photonic crystal waveguide with an integrated microheater.
Fabricating GaN on silicon wafers - Oki Electric Industry Co. has developed a technique to fabricate transistors of gallium nitride (GaN) on silicon wafers instead of expensive silicon carbide, reports the Nikkei English News. GaN-HEMTs (high-electron-mobility transistors) have good signal amplification properties for designing amplification circuits with fewer steps. This can help reduce both the space and power consumption of multichannel wireless communications systems. The problem is that GaN and silicon have incompatible crystal structures, so the transistors are now made on substrates of silicon carbide, which cost 50-100× as much as regular silicon wafers. Oki solved the crystal incompatibility problem by placing intermediate layers of aluminum and gallium-aluminum nitride between the silicon wafer and GaN layer on which the HEMT transistor gates are made.
Japan scientists make Braille rollable display - Researchers at the U. of Tokyo have created a flexible Braille display utilizing organic semiconductor devices, plastic actuators driven by an organic field-effect transistor active matrix. An underlying array of organic pentacene thin-film transistors with top-contact geometry was built on polyimide plastic substrates (20µm channel lengths, and mobilities of 1 sq. cm/Vs). Voltages are fed to actuators fabricated from conductive polymer, moving them upward and pushing attached hemispheres against the underside of the rubber-like surface film, forming bumps in the shape of Braille letters. Up to 24 letters on the entire 4x4x0.1cm device can be displayed. The device consumes about as much power (<1mW) as a cell phone or digital camera. Researchers hope to improve the display to show up to 576 letters of Braille at a time, with possible commercialization in 5-6 years, priced at 1000 yen (about US$8). - J.M.
A glimpse of 45nm at IEDM - At the 2005 IEEE International Electron Device Meeting (IEDM) last month, Intel provided a glimpse of the 45nm technology node in its paper on high performance CMOS transistors featuring fully silicided NiSi metal gates, uniaxial strained silicon channels, and 1.2nm SiON gate dielectric. The transistors feature drive currents of 1.57mA/μm for NMOS devices and 1.06mA/μm for pMOS. The transistors also exhibit on-off characteristics with low standby current of 100nA/μm for each structure. The metal gates were produced by diffusing metal into polysilicon during the low-temperature FUSI process, which avoids gate depletion effects and prevents metal from compromising the gate dielectric.
Also in the 45nm realm, Fujitsu presented a paper on overcoming issues of high junction-leakage currents and low drive currents in low operation power applications. To reduce leakage currents, the team used novel shallow trench isolation structures as well as strained silicon in the channel and SiON gate dielectrics. To reduce capacitance in the metal interconnect layers, they used a porous low-k oxide-based nano-cluster silica dielectric with a k value of 2.25 and employed a damage-free etching technique to maintain reliability. - P.L.