CMOS future involves new materials and devices
01/01/2006
Anticipating increased difficulty in scaling CMOS technology for ICs, the microelectronics manufacturing industry will continue to deploy new technologies that provide additional functionality in ICs. Some new technologies will be evolutionary additions to current CMOS processes. Others will be revolutionary and will go well beyond the theoretical limits of CMOS scaling. The International Technology Roadmap for Semiconductors (ITRS) proposes several “guiding principles” of materials and device requirements that provide directions for research.
James A. Hutchby, Semiconductor Research Corp., Research Triangle Park, North Carolina
C. Michael Garner, Intel Corp., Santa Clara, California
The relentless scaling of CMOS, having paced the microelectronics industry at the speed of Moore’s Law for the past 30 years, is rapidly approaching fundamental limits imposed by discrete atomic dimensions of critical materials (e.g., silicon-dioxide gate dielectric) and the quantum effects in conventional MOSFET structures. A broad array of new materials integrated into both conventional and new MOSFET device structures is being explored and developed to extend CMOS technology to its ultimate limit over the next 10-15 years.
Following the recent introduction of strained silicon into the channel of the MOSFET, new materials in R&D are focused on completely replacing conventional silicon-dioxide/polysilicon gate stacks in CMOS transistors with new high-k gate dielectrics and metal-gate electrodes. In addition to these materials, new device structures include a variety of silicon-on-insulator (SOI) single-gate and multiple-gate transistor designs. The newly completed 2005 ITRS concludes that highly innovative changes will be needed to extend more-or-less conventional CMOS technology down to the 22nm technology node and perhaps beyond.
High expectations for new devices
Fundamental R&D in materials science provides important clues to extending information-processing technologies beyond the anticipated maturation of CMOS scaling. To continue functional scaling, a new information-processing technology will likely be realized by the synergistic use of new materials embodying one or more new device structures that provide certain attributes:
- functional scalability several orders-of-magnitude beyond ultimately scaled CMOS;
- high information/signal processing rate and throughput;
- energy dissipation per functional operation that is substantially less than CMOS;
- manufacturability with a minimum scalable cost per function;
- room-temperature operation; and
- energy restoration to sustain steady-state operation (i.e., provide a gain mechanism).
Furthermore, any new technology should be:
- compatible with CMOS (functionally compatible architecturally or, ideally, technologically integratable with CMOS);
- stable and reliable; and
- insensitive to parametric variations and tolerant of defects and errors.
It is hoped that within the next 20 years these new device structures will be organized like conventional CMOS architectures. However, new architectural concepts may be needed to maximize the value of a novel information-processing technology in the longer term.
The 2005 ITRS Chapter on Emerging Research Devices (ERD) discusses and evaluates all leading candidates for emerging memory and logic technologies. The viability of each is assessed by the potential performance compared to ultimately scaled CMOS for logic and to the appropriate baseline technology for memory.
Several new candidates for memory applications have been identified as highly promising. These include nano floating-gate memory, engineered tunnel barrier memory, ferroelectric FET memory, and insulator resistance change memory. Conversely, no candidate technologies for logic applications, other than the 1D charge state (Fig. 1), are currently identified as promising, so significant research is needed to develop more radical logic devices.
Guiding principles
In considering the many disparate approaches proposed to provide order-of-magnitude scaling of information processing beyond that attainable with ultimately scaled CMOS, the ERD Working Group included a new section in the 2005 ITRS ERD chapter. This section summarizes the working group’s proposals for a comprehensive set of principles guiding research and development to continue order-of-magnitude scaling of information processing beyond that attainable with ultimate CMOS, using highly manufacturable fabrication processes. The following principles are necessary for a new “beyond CMOS” information processing technology to dramatically enhance scaling of functional density and performance while simultaneously reducing the energy dissipated per functional operation.
Computational state variables other than electron charge alone. These include spin, phase, multipole orientation, mechanical position, polarity, orbital symmetry, magnetic flux quanta, molecular configuration, and other quantum states. The estimated performance of alternative-state variable devices compared to ultimate CMOS should be made as early in the program as possible to narrow options and identify key tradeoffs.
Nonthermal equilibrium systems. These systems serve to reduce the perturbations of stored information energy in the system by thermal interactions with the environment. This function can be accomplished by systems that perform all computational processing functions in a time that is shorter than the system’s energy relaxation time. Due to thermal fluctuations at room temperature, energy barriers on the order of 10× KbT will be required to prevent random fluctuations of computational state in any bistable-switching device (where Kb is Boltzmann’s Constant and T is the effective temperature). One path to low-energy, room-temperature switching is to find systems that can operate out of thermal equilibrium with the phonon bath so the effective temperature for the system is less than the temperature of the general environment. Nuclear spin is a naturally occurring example of such a system.
Novel energy-transfer interactions. These interactions could provide the interconnect function between communicating information processing elements. Energy transfer mechanisms for device interconnection perhaps would be based on short-range interactions, including quantum exchange and double exchange interactions, electron hopping, Forster coupling (dipole-dipole coupling), tunneling, and coherent phonons.
Nanoscale thermal management. This challenge might be met by manipulating lattice phonons for constructive energy transport and heat removal. This technique would entail using phonon stop band structures for local energy redistribution and structures for nonisotropic heat transport.
Sublithographic manufacturing process. One example of this principle is directed self-assembly of complex structures composed of nanoscale building blocks. This requirement is essential to fabricate such blocks as quantum dots, semiconductor nanocrystals, metallic nanocrystals, and resonant cavities (metacrystals) in a bulk material capable of supporting the quantum interactions described previously (e.g., complex metal oxides). These self-assembly approaches should address nonregular, hierarchically organized structures, as well as be tied to specific device ideas and be consistent with high-volume manufacturing processes.
Many of these devices can be fabricated with existing process technology, but significant work must be done to extend IC technology beyond the limits of CMOS scaling. One category of work relates to extending CMOS by integrating, for example, a new high-speed, dense, and nonvolatile memory technology on the CMOS platform. Another involves replacing CMOS with innovative combinations of materials, devices, and architectural means for representing, transmitting, and storing information.
Challenges related to ERDs are divided into those related to memory technologies and those related to logic devices. One such problem is the need for a new memory technology that combines the best features of current volatile and nonvolatile memories in a fabrication technology compatible with CMOS process flow. This would provide a memory-device fabrication technology required for both standalone and embedded memory applications.
The development of electrically accessible nonvolatile memory with high speed and high density would initiate a revolution in computer architecture and provide a significant increase in information throughput. Such a development would transcend the ultimate nanoscale limits of CMOS devices. A longer-term challenge for information processing is invention and reduction to practice of a new manufacturable technology addressing beyond-CMOS logic applications. Solutions to this problem could open new opportunities for nanoelectronics.
Expanding the scope on new materials
Controlled material properties are central to the function of ERDs, and it will be necessary to structure these materials with required properties, assemble them in desired locations, and establish reliable high-performance interfaces (i.e., contacts, passivation, etc). The new Emerging Research Materials (ERM) section in the 2005 ITRS ERD chapter identifies the critical material properties and supporting capabilities for alternate-state variable devices.
Digital devices operate by representing information as one of the two or more possible values of a state variable, which is selectable by the operation of a stimulus. The operating characteristics of the device depend on the material properties and device structure. Currently known state variables include 1D charge state, molecular state (Fig. 2), spin state, and strongly coordinated electron state, among others. Each of these state variables can be changed when acted upon by one or more mechanisms.
Many of the new materials can be fabricated with existing process technology, but significant work must be done to control the structure, composition, and properties at the nanometer scale. Challenges for the fabrication of 1D charge-state devices include materials synthesis with tight control of properties and nanometer-scale precise location with any required orientation. Furthermore, forming reproducible electrical contacts and interfaces to these materials must be dramatically improved. The biggest challenges for molecular-state devices include fabrication with reproducible switching and transport properties, and validation that the transport is electronic switching of the molecule. The key challenges for spin-state devices are to identify ferromagnetic semiconductor materials with Curie temperatures above room temperature that are compatible with CMOS processing, as well as materials with properties capable of enabling spin gain in device structures. For materials with a strongly coordinated electron state, the issue is to determine whether the complex ferromagnetic and antiferromagnetic phase transitions and spin-charge-orbital ordering (observed in neutron diffraction for these materials) demonstrate room-temperature properties that could enable new device functionality.
Metrology to characterize the critical material properties and interfaces at the nanometer scale is a huge gap, according to the 2005 ITRS. Therefore, significant work is required to expand the capabilities of current metrology tools, such as atomic force microscopy, transmission electron microscopy, spectroscopy, etc., and to develop new test structures that can measure more state variable properties at the nanometer scale. Similarly, modeling and simulation capabilities must be enhanced and developed to enable separation of critical material and interface properties for assessment of their impact on device performance.
Conclusion
New information-processing device structures, based on novel materials, will be needed as the semiconductor manufacturing industry encounters increasing difficulty in shrinking nanometer-scaled CMOS. Though the requirements for new device structures are generally well known, developing the specific materials and processes necessary to repeatably form such structures remains challenging.
James A. Hutchby is the chair of the ITRS working group for Emerging Research Devices and director of device sciences for Semiconductor Research Corp. (SRC), Research Triangle Park, NC; e-mail [email protected].
C. Michael Garner is the chair of the ITRS working group for Emerging Research Materials and manager of external materials research in the external programs organization of the Technology and Manufacturing Group of Intel Corp., Santa Clara, CA; e-mail [email protected].