Roadmap requirements for emerging materials
01/01/2006
Anticipating increased difficulty in scaling CMOS technology for ICs, the microelectronics manufacturing industry will continue to deploy new technologies that provide additional functionality in ICs. Some new technologies will be evolutionary additions to current CMOS processes. Others will be revolutionary and will go well beyond the theoretical limits of CMOS scaling. The International Technology Roadmap for Semiconductors (ITRS) proposes several “guiding principles” of materials and device requirements that provide directions for research.
Mayank Bulsara, Atlas Technology Corp., Cambridge, Massachusetts;
George Celler, Soitec, Peabody, Massachusetts;
Ted White, Freescale, Austin, Texas;
Bob Standley, MEMC Electronic Materials, St. Peters, Missouri;
Howard Huff, Sematech, Austin, Texas
A significant section of the ITRS is written by the Starting Materials sub-Technology Working Group. In 2003, the Emerging Materials Committee was established within the Starting Materials Group to examine and track the alternative materials technologies under consideration for implementation in conjunction with traditional CMOS scaling. The 2005 ITRS includes the first full revision of the original 2003 Emerging Materials section.
The definition of emerging materials is as follows: Novel starting materials, structures, and processing methodologies that will enable anticipated Roadmap requirements and enhance silicon-based CMOS technology.
The Emerging Materials Committee identified three distinct categories of alternative materials solutions that are being examined by the semiconductor industry: mobility enhancement, thermal management, and system-on-chip (SoC) solutions.
Mobility enhancement solutions
High-mobility materials for enhanced transistor speed and reduced power consumption are critical for advanced CMOS applications. There are several approaches, including strain introduction and alternative materials (e.g., germanium, carbon nanotubes, and compound semiconductor channel layers), that are under consideration by the industry.
Strained silicon. Creation of elastic strain in silicon transistor channels is the most widely accepted method for enhancing the carrier mobility of Si. There are two variants of strained Si technology that have been demonstrated: 1) local strain engineering through transistor module optimization, and 2) global strain introduction through silicon-germanium (SiGe) epitaxial processes (and layer transfer processes for global strain with SOI). Local strain techniques are not considered “emerging” materials because they are already in production, but they serve as a reference point for the status and performance potential of global strain engineering techniques. Reported enhancements with local and global strain engineering techniques are shown in the table.
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Elastic strain in Si transistors creates the potential for strain-relieving defects such as dislocations and stacking faults. The introduction of functional microprocessors with defects in the strained pMOS transistors (Fig. 1) demonstrates that CMOS has a finite tolerance for crystalline imperfections. However, the understanding of the effects of defects within modern CMOS transistors is not complete, and further R&D is required.
Germanium. Transistors with Ge channels are being investigated for implementation in next-generation microelectronics. The ultimate advantage of working with Ge is potential carrier mobility enhancement, making it attractive for high-speed circuit applications. Low field, bulk electron mobility in Ge is more than double that of Si (3900 vs. 1500cm2/V-sec) and the increase is fourfold for holes (1900 vs. 450cm2/V-sec). It should be noted that although low field, Hall mobility in bulk material is a good indicator of the potential benefits for CMOS, the mobility enhancements in inversion layers at strong gate overdrive determine the actual benefits for CMOS application.
Despite the intrinsic speed advantages of implementing Ge transistor technology, Ge does not grow a stable oxide, so traditional MOS manufacturing methods for gate electrode formation cannot be used. Germanium oxynitride [2, 3], aluminum oxide [4], hafnium oxide [4], and zirconium oxide [5] high-k dielectrics have been implemented with Ge channel transistors with varying degrees of success. However, as with the integration of high-k gate stacks with Si, no completely satisfactory solution has been demonstrated with Ge. This, in part, has led to less than anticipated mobility enhancements for electrons and holes in Ge MOSFETs.
There are generally three embodiments of Ge substrate technology: 1) bulk Ge substrates, 2) Ge layers transferred to oxidized Si handle wafers, thereby forming Ge-on-insulator (GeOI), and 3) epitaxial deposition of Ge thin films on Si substrates. Bulk Ge substrates (grown via the Czochralski method) are more difficult to fabricate than bulk Si substrates due to the lower critical resolved shear stress and lower mechanical strength of Ge. Although 300mm dislocation-free Ge substrates can be fabricated, the economics of high-volume manufacture is still unsure. Ultimately, even if the technical and economic issues were resolved, it is unlikely that the world’s Ge reserves could support the complete replacement of bulk Si with bulk Ge, so it is expected that GeOI is the preferred substrate embodiment. Epitaxial Ge technology is especially promising for the implementation of strained Ge channels.
Surface and channel orientation. Another approach to improve on the mobility and current drive capabilities of Si involves the exploitation of the mobility anisotropy of Si. Figure 2 shows the mobility of electrons and holes for different surface orientations, and in the case of the (110) surface, two different in-plane channel directions. It is well known that electron mobility is highest for the traditional Si substrate/transistor configuration, a (100) surface with a <110> channel direction, while hole mobility is highest for a (110) surface with a <110> channel direction. Recently, a hybrid substrate configuration [6] has been proposed to allow for the ultimate mobility configuration for each carrier.
 Figure 2. a) Electron and b) hole mobility anisotropy in Si allows for charge carrier mobility improvements through channel orientation. (Source: IBM) |
It should also be noted that even without a change in surface orientation from the traditional (100) surface, hole mobility has been reported to increase by rotation of the channel direction 45° from the <110> direction to the <100> direction [7-9]. This effect has been reported to be utilized in 90nm-node products [1].
As with conventional Si surface and channel geometries, the use of strain in tandem with different substrate/channel orientations is under investigation [10, 11].
Carbon nanotubes. Carbon nanotube (CNT) field-effect transistors (CNTFET) can be modified and controlled in many of the same ways that Si MOSFETs can be tailored. They can be p-type or n-type, and their threshold voltages can be set by doping. CNTFETs can exhibit bulk-switched behavior like MOSFETs with characteristics equal to or superior to conventional Si devices. The advantages of CNTFETs include high mobility, minimal mobility degradation when integrated with high-k dielectrics, ballistic transport, adjustable bandgap, and low contact resistance. Integration of CNTFETs has also been shown viable through demonstration of NOT and NOR logic gates, flip-flops, ring oscillators, and voltage inverters.
 Figure 3. Carbon nanotube FET structures may improve the performance of nanometer-scale ICs. (Source: IBM) |
CNTFETs are 1D devices due to the small diameters of CNTs (Fig. 3). The 1D nature of CNTFETs draws performance comparisons to Si nanowire FETs, which have exhibited superior scalability over even double-gate FETs in simulations [12]. CNTs offer several advantages over Si nanowires. They are about 5× thinner than the thinnest Si nano-wires, leading to improved scalability. Si carrier mobility degrades, especially for holes, as the Si becomes thin [13], whereas this is not the case for CNTFETs, which have hole mobilities up to 80× higher and lower self-heating than in Si nanowires with comparable dimensions [14, 15]. CNTs also have atomically smooth surfaces for hundreds of microns and all the carbon bonds are within the CNT, reducing electronic states at the interface with the gate dielectric. These features allow for ballistic transport and higher on-currents than Si nanowires [14-16].
While CNTs are very attractive for use in extremely scaled ICs, methods must be developed to precisely and consistently control the structure (e.g., desired positions, helicity, diameters, and lengths), and thus the electrical properties, of CNTs during synthesis.
Thermal management solutions
Material solutions are being examined to enhance the thermal conductivity within CMOS circuits, thereby mitigating potential hot spots and overheating of circuits.
Layer-transfer technologies for enhanced thermal properties. Materials with higher thermal conductivity than Si in the immediate vicinity of the transistors could potentially keep circuits cooler because of their more efficient heat removal. For example, single-crystal diamond and single-crystal silicon carbide (SiC) have thermal conductivities of 20W/cm-K and 3-4W/cm-K, respectively, that are much greater than that of Si, 1.5W/cm-K. The transistor regions need to be placed on top of either a handle wafer consisting completely of higher thermally conductive material or a high thermal-conductivity layer that itself resides on top of a conventional Si substrate. In the second case, heat removal from the active circuit is not significantly changed, but heat can be spread more uniformly to reduce hot spots.
 Figure 4. Opportunities for improved thermal management in silicon chips. |
Combining CMOS-quality Si with either diamond or SiC, most practically in polycrystalline form, requires wafer bonding and layer transfer. Such a structure would be similar to SOI, but with a considerably thicker layer of diamond that facilitates lateral heat flow (Fig. 4). It is difficult to obtain a smooth surface of polycrystalline diamond, so a planarizing layer of polysilicon or SiO2 may be needed between the Si film and the diamond. A SiO2 layer would also help passivate electrical defects at the lower Si interface. For SiC, an oxidized layer of Si can be transferred to a polycrystalline SiC wafer.
The insulator in SOI structures is normally a thin layer of thermally grown SiO2. Aluminum oxide (Al2O3) has a thermal conductivity 10-30× higher than SiO2 and is a candidate insulator material to improve heat dissipation during SOI circuit operation.
SoC solutions
Incorporating material properties that aid processing of radio-frequency (RF) signals or enable light emission/detection capability with Si are considered important paths to enable SoC functionality with CMOS.
High-resistivity silicon. Most CMOS logic and memory circuits are fabricated on wafers with 1-20Ω-cm resistivity. The integration of RF functionality with CMOS favors a shift to a very high substrate resistivity ≥~1000Ω-cm, although in practice, resistivity >50Ω-cm offers tangible performance benefits.
Production of high-resistivity Si places three stringent demands on the crystal growth process. First, the intentional dopant addition to the crystal must be very tightly controlled to produce extremely good axial and radial resistivity uniformity. Second, the sources of unintentional doping must be minimized by the careful use of high-purity materials. Finally, the formation of interstitial oxygen (Oi)-related thermal donors during heat treatment in the temperature range of 400-550°C (common in backend fab processes) must be suppressed. Currently, the most promising approach to suppress thermal donor formation is to deliberately grow oxygen precipitates in the wafer in order to consume Oi [17] while still maintaining control of the requisite wafer warpage.
Conclusion
Emerging materials may augment Si transistor technology by providing enhanced speed, improved heat dissipation, and/or added functionality. Multiple paths now exist that are anticipated to lead to further CMOS benefits. A full version of the ITRS Emerging Materials report can be found at http://public.itrs.net.
Acknowledgments
The committee is grateful to the following industry experts who presented information on several relevant topics: Steve Burden, Isonics; Minjoo Lee, MIT; Geoffroy Raskin, Umicore; Joerg Appenzeller, IBM; and Devin MacKenzie, Kovio.
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Mayank Bulsara chairs the ITRS Emerging Materials Committee, and is president of Atlas Technology Corp., a consulting firm focused on evaluation and development of emerging semiconductor technologies; e-mail [email protected].