Building engineered substrates for GaN HEMT applications
01/01/2006
Compound semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP) are key materials in high-frequency and optoelectronic devices. New or evolving applications pave the way for further performance requirements, particularly for high-frequency, high-power, or optoelectronic applications. Materials in the III-nitride category are recognized as the potential response to these new demands and one example - GaAlN/GaN high electron-mobility transistor (HEMT) devices for microwave power applications - has been studied for some time. This article discusses how layer transfer technology has been demonstrated to be appropriate for building specific engineered substrates for GaN HEMT applications.
P. Bove, H. Lahreche, Picogiga Int., Courtaboeuf, France;
B. Faure, F. Letertre, A. Boussagol, R. Langer, Soitec, Crolles, France
Silicon, long the main material used for IC manufacturing, is still the usual choice. However, silicon material constraints have been clearly identified for specific advanced applications, and new materials have been used to overcome them. In particular, defense radar and wireless communication systems have a significant need for increased performance, especially for high-power, high-efficiency, high-linearity, and low-cost monolithic amplifiers operating in the 1-40GHz frequency microwave power range.
Results reported over the last three years, including high breakdown electric field, high electron mobility, and high saturation carrier velocity, have identified GaAlN/GaN as an emerging path for high-power devices. A high breakdown electric field allows operation at higher voltage, which means that at the same power level it is possible to achieve much higher matching impedances, lower power recombination losses in multitransistor amplifiers, and better energy efficiencies in less complex circuits. The intrinsic high thermal stability of the material should allow operation at higher temperatures, requiring a less stringent (and less expensive) thermal management solution for packaging high-power amplifiers. High-temperature operation, however, will be attained at the cost of microwave performance (i.e., gain, output power). Therefore, because of the very high power density of GaN devices, it is necessary to explore thermal management issues.
Recent advances in molecular beam epitaxy (MBE) growth of GaN on high-resistivity, low-cost Si substrates (up to 4 in.) and reliability results on devices are presented here. Additionally, an emerging low-cost solution is presented that uses engineered substrates (created with a layer-transfer technology) as an alternative to expensive plain SiC single-crystal substrates. These alternatives are driven by the need for a cost-effective solution that provides high-quality GaN-based active layers on high thermal-conductivity substrates. The layer-transfer technology allows the combination of materials with different natures and properties, creating an engineered multilayered structure. Combining Picogiga’s MBE knowledge and Soitec’s Smart Cut layer-transfer technology, the proposed substrates are GaN-on-silicon, SiC-on-insulator (SiCOI), GaN-on-insulator (GaNOI), and Si-on-polySiC (SopSiC).
MBE growth of GaAlN/GaN HEMT
Epitaxy growth process. Using gas-source MBE with ammonia as the nitrogen source, Picogiga has developed a reproducible growth process for GaN-on-Si substrates. The advantages of using high-resistance (HR) Si arise from its crystal quality; the availability of large, cost-effective substrates; its high resistivity property; and the large body of knowledge concerning its surface preparation. Reproducibility of initial growth stages onto the HR Si (111) surface enables reproducibility of the GaN crystal quality. MBE has proved its ability to fulfill production requirements for GaAs and related materials for a wide range of microwave devices and is being extended to the nitride field. Different generations of GaN epitaxy structures on HR silicon have been developed (and will be referred to as SPX structures later).
The standard specification known as Structure Piezo 1 (SP1) is a purely piezoelectric structure: The 2D electron gas is created by a piezo-injected electron from the GaAlN barrier into the GaN channel. No doping is used in the structures. This process enables reproducible mobility and electron density.
The GaN template (typically 1.5µm thick) is naturally highly resistive (>106Ω-cm) with low threading dislocations (TD), typically 3-5×109/cm2. A new structure - called SP2 - with an improved GaN/GaAlN interface was recently proposed. With this new structure, the mobility of the 2D electron gas is increased by 30% (Fig. 1).
The standard sheet resistivity values for SP1 and SP2 are 400Ω-cm and 300Ω-cm, respectively, which correspond to electron mobilities in the 1500cm2/V-sec and 1900cm2/V-sec ranges, respectively. By increasing aluminum content up to 35%-47%, it is possible to decrease sheet resistivity down to 260-280Ω-cm (Fig. 2).
 Figure 2. Sheet resistivity cartography of a 4-in. SP2 structure with 30% aluminum showing a 1.33% standard deviation. |
Surface characteristics. To examine the typical morphology of SP1 and SP2 structures on HR Si (111) substrates, photographs using atomic force microscopy (AFM) were taken. The surface is very flat (a typical peak-to-valley height in a 15×15µm scan is 25nm). For this reason, the z scale was increased by a factor of 10 on the second image. The rms roughness is typically 3-5nm on 15×15µm scans. Atomic steps are clearly visible (height = 0.259nm) as well as TDs that are in the 109/cm2 range (typically 5×109/cm2). A study is ongoing to compare TD densities measured by TEM and AFM. Figure 3 is an example of a typical x-ray diffraction scan for an SP2 structure. The quality of the interface is demonstrated by the strong interference fringes for low angle values.
Device results. SP1 structures were processed during collaborations with different partners. RF results are summarized in Table 1. The maximum power density reported is 7W/mm at 10GHz, associated with a power-added efficiency (PAE) of 39%. The maximum PAE was 52% at 3.9W/mm for the same device. Better results are expected using structures with improved mobility.
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First reliability results. Reliability studies were performed on SP1 structures. The device is a 1µm-long gate with two 150µm fingers. Passivation is realized with SiN/SiO2. The transconductance of the devices is 120mS/mm. In initial studies, devices were stressed with VGS = 0V, VDS = 20, and with continuous bias voltage without cooling the system. The resulting power density was 9.33W/mm. After 90 hr, the resulting ID drop was <3% (Fig. 4) and the variation in IG was <10%.
 Figure 4. Aging test on an SP1 HEMT device (IG, ID normalized as a function of time). |
The ID and IG curves illustrate the “drain lag” and “gate lag” issues. To help determine the origin of the ID decay in the charge trap in the insulating area, measurements of the insulating properties of the buffer were taken (Fig. 5). Current leakage measurements have shown values minimized to 10µA, and the buffer’s insulating behavior was tested with mercury probe tools: CV measurements show abrupt pinch-off, and background doping level (measured just after pinch-off) is measured at a low range of 1.5×1014/cm3. The increase of doping observed after pinch-off corresponds to the interface between the GaN and Si substrates. No leakage was observed after processing this layer. The IG decay is still under investigation for the case where the electron trap is on the drain side of the gate.
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Thermal management: Substrate approach
In the work that was done to develop low-cost alternative substrate solutions for III-N materials, two contradictory objectives were tackled: 1) lowering the substrate cost of high-end solutions based on the single-crystal bulk SiC material properties (semi-insulating, high thermal conductivity, high-quality seed material for GaN growth), and 2) improving the performance of low-end silicon-based solutions.
Since the MBE growth technique of GaN piezoelectric structures is already well established and demonstrated, as reported previously, the materials roadmap used for these activities is aimed at developing materials that can improve substrate behavior without jeopardizing the performance of the GaN structures. Layer transfer technology emerged as the enabling approach to realize composite substrates that support the roadmap; the technology allows the transfer of a thin layer of one material onto a base substrate made of another material, thus allowing independent optimization of the front- and backsides for further use of the substrate.
SiC-on-insulator substrate. A SiCOI substrate is composed of a monocrystalline SiC thin film handled by a base substrate through an intermediate insulating layer, usually SiO2. SiCOI structures are built by using the Smart Cut layer method [4]. The technique uses hydrogen ion implantation into an oxidized SiC substrate, then wafer bonding of the implanted SiC substrate to the receiver substrate, also called the base substrate, and finally, transfer of the SiC thin film, where thickness is defined by the ion-implantation step energy. Wafer bonding is achieved between the oxidized SiC substrate and the receiver substrate through specific surface preparation and cleaning techniques.
This technology is compatible with any monocrystalline SiC polytypes (e.g., 6H, 4H, 3C). There are also no limitations in terms of electrical resistivity and crystal orientation. Thus, either semi-insulating or low-resistivity, as well as on-axis or off-axis SiC crystals can be successfully split from a bulk substrate and transferred onto a receiver substrate. The thickness of the SiC transferred thin film varies from 0.1-0.8µm. For intermediate buried oxide, the thickness usually varies from 0.2-3µm. The receiver substrate can be chosen according to final desired properties - for example, SiC can be transferred onto HR Si for cost and electrical property advantages or polycrystalline SiC for electrical property and thermal conductivity advantages. The technology also makes it possible to use reclaimed SiC wafers, already used for a first transfer, so the same SiC donor wafer can be used several times (typically 5-10 times).
SiCOI substrates have been widely characterized for either 6H or 4H thin films transferred onto silicon or poly SiC [4]. In this particular study, SiCOI substrates with a 300nm-thick on-axis 6H SiC thin film on a silicon handle substrate with 500nm-thick silicon oxide buried layer were investigated.
Si-on-polycrystalline SiC. It has been understood that bulk high-purity (111) silicon may encounter some limitations for high-power applications due to its low thermal conductivity (Table 2). By using engineered substrates made of a thin film of Si (111) bonded onto a polycrystalline SiC (pSiC) substrate, GaN HEMT structures can sustain much higher power levels because of the improved thermal dissipation properties of the substrate.
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SopSiC substrates have been built using the process described previously. Already demonstrated in large-volume industrial applications for silicon-on-insulator (SOI), the initial characteristics of the silicon material are fully maintained across the process. The carrier substrate is made of semi-insulating polycrystalline SiC with a resistivity >105Ω-cm. The surface roughness of the pSiC wafer is particularly important for the quality of the bonding and has been extensively studied.
 Figure 6. GaN junction temperature for various structures and power levels. |
Thermal behavior of a SopSiC substrate has been simulated to investigate the effect of various parameters such as the thickness of the insulating intermediate layer, its nature, the thickness of the transferred silicon layer, and the power dissipated by the devices. Significant results are reported in Fig. 6. An improvement in junction temperature increase (with the case at room temperature) is observed for SopSiC substrates compared to bulk silicon substrates, which is even more visible when the power level of the device is in the high range. Figure 6 shows that the SopSiC substrate, even if not performing as well, is marginally worse than the bulk monocrystalline SiC. This confirms that the layer transfer-based composite substrates are promising for high-performance, low-cost RF power applications of GaN HEMT structures. Bow and wafer warpage measurements show that the SopSiC substrates are able to sustain any processing steps required for HEMT processing; these parameters are essentially driven by the initial pSiC substrate characteristics.
So far, SopSiC substrates have been shown for 2-4 in. dia., but can be extended to 6 in. since the layer transfer technology is used for high-volume manufacturing in 200mm and 300mm wafer sizes. Also, pSiC and FZ HR Si (111) substrates are available in 6 in. It also has been demonstrated that an MBE process for GaN-based HEMT structures used on Si (111) bulk substrate can also be used on SopSiC substrates because the seed layer remains Si (111) [5].
GaN-on-insulator substrate. GaNOI was fabricated using the Smart Cut technology to slice a monocrystalline layer from a bulk GaN substrate, then transferring and bonding it onto an insulating substrate made of poly SiC or HR Si, substrate. This represents the ultimate step in enabling homoepitaxial growth of the best-quality GaN films. As for silicon or SiC, the original GaN bulk substrate can be chosen with different properties, such as semi-insulating or semiconducting. However, this technique is limited by the availability of high-quality GaN bulk material, which remains expensive and only available for 2-in. dia. wafers. Moreover, GaN bulk is not yet completely suited for the wafer bonding process, and, currently, some specific surface treatment on the backside of the substrates (n polarity) is a necessity along with polishing to obtain flatness and surface roughness. GaNOI development is in hand, but cannot be produced in high manufacturing volume.
Conclusion
Layer-transfer technology has been demonstrated to be appropriate for building specific engineered substrates for GaN HEMT applications. SiCOI material is available for cost-effective, high-end applications, allowing GaN HEMT layer quality to be state-of-the-art and comparable to that obtained on bulk monocrystalline SiC substrates.
SopSiC substrates have been demonstrated up to 4-in. dia. GaN epitaxy structures have been grown by MBE, using the same process as that for growing structures on bulk single-crystal silicon. Thermal simulations show that SopSiC substrates will behave similarly to bulk semi-insulating SiC and will drastically improve the maximum power levels sustainable by GaN-based HEMT structures for RF power applications. Due to the large-scale availability of pSiC material, substrates up to 150mm dia. can be available in a relatively short period of time.
To further enhance the overall performance of GaN HEMT structures, R&D has already started to investigate the potential use of the layer-transfer technology for manufacturing composite substrates made of a thin GaN monocrystalline layer bonded onto a polycrystalline semi-insulating SiC substrate (GaNOI on pSiC). This product will potentially leverage the electrical performances of the GaN structures (by growing MBE layers on GaN material), while keeping the thermal conductivity of the substrate very high, due to the use of pSiC material. This study will be further conducted in conjunction with the development and availability of GaN single-crystal growing techniques.
Acknowledgments
The authors would like to thank S. Delage and D. Pons from Thales Research Technology and the European Community through their support in the Euronim contract; S. Bressot from Soitec S.A. for her contribution to engineered Smart Cut substrate fabrication; and D. Da Cruz from Picogiga Int. for his contribution to GaN epitaxy development on silicon. Smart Cut is a trademark of S.O.I.TEC Silicon On Insulator Technologies.
References
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Philippe Bove is R&D director at Picogiga Int., Place Marcel Rebuffat, 91971 Courtaboeuf, France; e-mail [email protected].
Bruce Faure is R&D project leader at Soitec S.A., Parc Technologique des Fontaines, 38926 Crolles Cedex, France; e-mail [email protected].