Will 3D keep the chip industry rolling?
12/01/2007
There may be trouble ahead for the conventional shrink approach to Moore’s Law. Lithography looks dicey for 32nm (which might be reached through dual imaging with improved 193nm immersion stepper/scanners), and even trickier for 22nm. Even if EUV surmounts remaining technical hurdles, there are concerns about cost and productivity. While some believe nanoimprinting offers promise, defectivity may spoil the party. Aside from lithography issues, some experiments suggest that even with the best technical efforts there may be no performance difference between 32nm and 22nm half-pitch chips. If so, why make the huge investments to reach 22nm?
When traditional transistor scaling began to fail, chips were speeded up by using stressed lattice silicon to boost carrier mobility. That interim solution, even with metal gates and higher-k gate dielectrics to gain improved equivalent oxide thickness (EOT) under the gate, appears to lose steam below 32nm. Interconnect delays were cut by going to copper for better resistivity, and low-k dielectrics to improve the C of the RC time constant. But ever thinner copper traces, and trouble with mechanical strength and delamination of low-k dielectrics, spell trouble below 32nm.
Maybe the industry will find miraculous cures for all these red brick walls-it’s happened before! But the physics gets progressively more constraining, and potential solutions involving new materials, processes, and more intricate process tools to continue the shrink will significantly increase fab costs. (Costs are already getting too high for even some major integrated device manufacturers.) Even if solutions are found, experience shows that the tougher the problems, the longer it takes to find practical, economical solutions.
Could stacking and bonding thinned chips (or even wafers) provide an alternate way to keep driving down the cost/function? Conventional stacking is widely used already, but connecting only around the edges of the chips creates long trace paths, degrading performance. A much better approach would be to use through silicon vias (TSVs), allowing shorter traces, and, with clever layout, perhaps even improving performance compared to putting all the circuits onto one chip. That potentially could provide a packaging approach to 3D integrated circuits with much higher apparent density than is possible on one chip. Even beyond that, it might be possible to build up layers of interconnected circuits on the same substrate, making true 3D ICs, an approach Samsung demonstrated for flash memory at the last IEDM.
Development work on TSVs, bonded thin wafers and chips, and multichip packages has been going on for a long time. But taking advantage of the full potential of 3D approaches would require much more intensive R&D, not just for laboratory demonstrations, but for practical, economical, high productivity fab and packaging processes. Heat is already a problem on single chips, but thermal problems would become much more serious in a high performance chip stack. Taking full advantage of 3D would require new approaches to chip design, new design automation software, lower cost ways to drill or etch out TSVs and fill them, ways to deal with hot spots (especially inside the stack), and methods for testing with most contacts inaccessible. Failures might occur during stacking and bonding even if known good die are used, cutting yields.
All the chipmakers are exploring the potential for 3D, and see these techniques as a way to keep increasing circuit density even if it takes too long to get to 22nm, or it proves too tough and expensive. Sematech has been driving the push toward 3D, and, as it prepares to move the work to its branch in Albany, NY, it held a workshop there to explore 3D design and thermal issues. There were about 75 attendees, and presentations outlined the myriad potential problems and possible solutions to move ICs into a third dimension. Since everything from system design to circuit and device design, to interconnect and layout, plus packaging and testing, must be considered, this area will require a multidiscipline approach without the turf wars and “throw it over the wall” attitudes of the past.
Once the practical problems are worked out, new approaches to functionality and system architecture capitalizing on the 3D form factor could go way beyond the multicore, multithreading techniques now emerging to deal with performance limits and thermal constraints.
One speaker who teaches university classes commented that he told his students they were extremely lucky to be getting into a field like this just as it is taking shape. There should be exciting times ahead for those working on 3D ICs.
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Robert Haavind
Editorial Director