Technology news
12/01/2007
Toshiba: Greener copper clean lowers costs, improves yields
Using HCL, HF and choline for cleaning copper vias after etch dramatically cuts both costs and environmental impact while improving yields, reports Toshiba Semiconductor Co.’s Yoshihiro Uozumi in SST partner Nikkei Microdevices. The simple common chemicals cost as little as 1/30 as much as some complex commercial removal chemistries, and can be easily treated on site with the fab’s existing waste water management system.
Toshiba’s previous commercial cleaning solutions typically contained a complex mix of organic solvents, fluorine compounds, surfactants, and chelates that couldn’t easily be separated out for separate treatment, says Uozumi, so had to be hauled away in trucks for specialty incineration, which consumed energy and added to costs. Because these materials were so expensive, they were typically recirculated through the cleaning equipment, eventually accumulating particles that caused defects.
 Fig.1. Residue remaining within and around the vias after etching is effectively removed by cleaning with HCL and HF. (Source: Toshiba, Nikkei Microdevices) |
Researchers investigating the problematic residues left at the bottom of the vias after etching found that most of the yield problems were caused by copper fluorides, copper oxides, and silicon oxides. So they looked for high-purity chemicals already being handled in the fab that could remove these materials without damaging the copper. The new method first uses dilute HCL to remove the copper impurities [e.g., CuOx and CuF4], then dilute HF to remove the silicon impurities like SiOx (see Fig.1). Post rinsing with pure water did not remove all the CL and F, which gradually formed an oxide film on the copper surface that increased sheet resistance. So the copper surface is stabilized after cleaning with the dilute amine choline [(CH3)3N(CH2)2OH]OH, which Toshiba used in its FEOL process. Without the choline rinse, sheet resistance increased 1% in four hours-with the rinse there was no increase after 100 hours.
All these chemicals are very cheap and readily available. Using existing effluent management systems saves transportation and waste treatment expenses, and getting better performance from existing equipment saves on equipment upgrade costs as well.
 Fig.2. New cleaning process improves yield in problematic perimeter region of wafer. (Source: Toshiba, Nikkei Microdevices) |
Uozumi also reports the new cleaning process has improved yields from the levels Toshiba was getting with commercial chemistries. When the company first introduced copper interconnects using available cleaning solutions, as many as 10 of the 18 chips in the problematic outermost perimeter row around the wafer were bad. With other commercial cleaning products the company could get that down to 5 bad chips in 18 (see Fig.2), though longer cleaning times merely tended to damage the via sides and enlarge the diameters. With the current low-cost cleaning process, there are zero defects on most wafers, apparently due to more complete removal of the etching residue, and fewer components and particles left behind from the cleaning solution.
Stress migration tests in via chains of 1 million units at 250°C for 1000 hours found almost no change in via resistance. Resistance to electromigration from level to level at 325°C met Toshiba standards. -P.D.
Molecular Imprints touts imprint litho for 22nm CMOS
In what it claims is validation for imprint lithography for 22nm CMOS, Molecular Imprints Inc. (MII) is touting results from Toshiba, reported at the 33rd International Conference on Micro-and Nano-Engineering (Copenhagen, Denmark, Sept. 23-26), which show defect levels “very similar” to those seen in the early days of immersion lithography’s introduction.
Using step-and-flash imprint lithography (S-FIL), Toshiba says it was able to achieve isolated 18nm features with <1nm critical dimension uniformity (CDU), and <2nm line-edge roughness (LER), and the defect density from all sources on a full-field imprinting tool (depending on the measurement system’s sensitivity) ranged from a little over 5 to ~0.3/cm2. “These are defect levels that were very similar to where immersion lithography was at the same stage of its introduction into use,” said Mark Melliar-Smith, MII’s CEO, in a briefing with SST. Toshiba also achieved results for 24nm dense lines and spaces, structures used to investigate advanced memory structures.
The overlay (OL) reported was 20nm, 3σ, mix-and-match (i.e., not single tool), which represents “very rapid improvement,” noted Melliar-Smith. “We’re looking to driving the OL down to whatever the industry will need a couple of MII’s end users view OL as the ‘long pole in the tent.’”
The data was obtained on MII’s Imprio 250 system, which was delivered to Toshiba in January, installed by the end of March, and accepted in <10 weeks, according to Melliar-Smith. “In my mind, that’s a very commendable schedule for a first tool in a pretty complicated technology such as they are fabricating,” he said, adding that moreover, “it demonstrates to the world the ease of use of the core imprint technology.” He further noted that MII delivered a complete system (tool, sources, materials, process) and the company has received infrastructure support from the rest of the industry, citing the fact that all the imprint masks were provided by DNP.
Readiness for the 22nm design node, when some do not expect EUV to be ready, is a key issue. “We’re in this business because we believe we have the best NGL solution bar none, and our intention is to have high-volume manufacturing tool capability with all the requirements (i.e., defects, resolution, throughput, CoO, infrastructure, etc.) available for when the industry needs it,” said Melliar-Smith. He thinks the 22nm design node is a good estimate for when NGL will be required, and he told SST that the likely choice will be imprint lithography, noting that several of the challenges facing EUV are much higher-risk than those facing imprint lithography.
This latest news about Toshiba’s work at 22nm follows an earlier announcement that MII received a fourth order for its whole disk imprinter tool (for HDDs) (Imprio 1100), representing a third different end user for the system. This technology is geared for dimensions of 20nm and below, which are typically isolated squares, i.e., contact “windows.” “We see this as a very big market,” said Melliar-Smith, noting that developing and selling tools into this industry is synergistic with CMOS. “The tools are the same, the templates are made with the same sort of technology, the processes are very similar,” he said. The difference between the two applications is that one uses a whole wafer tool and the other a step-and-repeat tool. -D.V.
Silicon quantum dots promise solar cell efficiency boost
Efficiency is one of the biggest challenges for solar cells: most of the sun’s incoming light is dissipated as heat, not converted to electricity. Yet researchers think the strange behavior of tiny particles known as quantum dots may help break the efficiency barrier. In quantum dots, energy that might otherwise be lost can excite additional free carriers.
Though the sun bathes our planet in about a thousand watts of energy per square meter, the best silicon solar cells achieve efficiencies of only about 24.7%[1]. (All efficiencies quoted in this article are for individual cells. Fully integrated modules suffer additional resistive losses.) The maximum possible efficiency, the Shockley-Queisser limit, is only about 31%[2]. After decades of effort, conventional silicon cells are approaching their theoretical limits.
One of the main reasons for the Shockley-Queisser limit is the mismatch between the energy of incoming photons and the band structure of the cell. If a photon has more energy than needed to generate a free carrier, the excess energy is lost: it simply dissipates as heat. If a photon has less energy than the band gap, it fails to excite a carrier, and its energy is also lost as heat. Since only a small fraction of the sun’s output lies precisely at the silicon band gap, substantial energy is lost through mismatch alone.
One partial solution, the so-called tandem cell, stacks several junctions, each with a different band gap. Though the Shockley-Queisser limit applies to each junction individually, combining junctions allows the cell to capture a larger fraction of the sun’s output. At this writing, the world’s record for cell efficiency is 40.7%, held by a multi-junction cell based on gallium arsenide.[1] Still, tandem cells don’t address the basic problem of supra band gap photon energies. They still dissipate the excess energy of such photons as heat.
A phenomenon known as impact ionization may be able to help. In impact ionization, hot carriers generated by a high-energy photon transfer some of their energy to another carrier, exciting it to the conduction band and creating an electron-hole pair (see figure). In bulk materials, impact ionization is rare. There simply aren’t enough such events to offset electron relaxation back to the conduction band.
Carrier confinement in quantum dots produces a number of useful effects, however. First, as Eun-Chel Cho and coworkers at the U. of New South Wales explained, restricting at least one dimension to less than the Bohr radius of silicon increases the band gap. In a closely spaced array, where all three dimensions are constrained and the wave functions of adjacent dots overlap, the band gap depends on the spacing of the resulting super-lattice. Thus, a material with arrays of embedded quantum dots of various dimensions functions as a tandem cell, capturing several slices of the total solar spectrum.[3]
Second, and even more interesting, as Antonio Luque of the Polytechnic U. of Madrid explained, the carrier confinement increases interaction between electrons and holes, greatly increasing the impact ionization rate. A single photon can generate two or even three or more photocarriers. Though not all will ultimately contribute to the photocurrent, calculations from the Shockley-Quiesser model put the maximum theoretical efficiency for quantum dot solar cells around 45%.[4] As in tandem cells, this limit would apply to each sub-array separately, so the total efficiency could be higher.
Multi-exciton generation is not a new phenomenon, having been demonstrated in PbSe, PbS, and PbTe over the last several years. (See references to [4]) More recently, though, studies of silicon quantum dots have shown that this most ubiquitous of semiconductors can achieve multiple exciton generation as well. Using silicon allows manufacturers to deploy the full array of silicon deposition and patterning technologies, while still working with a much more environmentally neutral material than lead.
According to Cho, alternating layers of silicon-rich and silicon-poor dielectrics can be annealed to create a super-lattice. Annealing precipitates quantum dots out of the silicon-rich phase, while the dielectric phase isolates successive layers from each other.
Though this work is interesting, it doesn’t mean that we should expect 40% efficient silicon cells anytime soon. Actually extracting carriers from quantum dots into the circuit is difficult. Quantum dots, by definition, are completely surrounded by insulating materials-a direct conducting path would break the confinement responsible for their special properties. To escape, each carrier must make a series of tunneling steps, jumping from one quantum dot to the next until it reaches the cell’s electrodes. The odds against such a trip increase with distance. Rather than placing a grid of electrodes above and below the super-lattice of quantum dots, a more effective design might intermingle quantum dots with a low conductivity semiconductor, such as a conjugated polymer semiconductor. The polymer’s low conductivity preserves the dot’s isolation, while providing a direct connection to the cell electrodes.
Luque cautioned that such designs remain hypothetical at this point. Though photovoltaic effects have been seen in quantum dot-polymer hybrid cells, and spectroscopy has confirmed the existence of the MEG effect, no quantum cell design has yet demonstrated that “extra” MEG carriers can be extracted to the circuit. Quantum dot cells offer exciting potential, but also enormous uncertainty. -K.D.
- M. A. Green, et. al., “Solar cell efficiency tables (version 30),” Prog. in Photovoltaics: Research and Applications, vol.15(5), pp 425-430 (2007)
- W. Shockley and H.J. Queisser, J. Appl. Phys., vol.32 (3) (1961) p. 510.
- Eun-Chel Cho, et. al., “Silicon quantum dots in a dielectric matrix for all-silicon tandem solar cells,” Adv.OptoElec., vol. 2007, article 69578.
- Antonio Luque, Antonio Marti, and Arthur J. Nozik, “Solar cells based on quantum dots: multiple exciton generation and intermediate bands,” MRS Bulletin, vol.32, pp 236-241 (March, 2007).
Immersion lithography reaches new heights at CO symposium
Attendees at the International Symposium on Immersion Lithography (Oct. 8-11, Keystone, CO) heard that three types of 193nm water immersion exposure tools are being used for mass production: Nikon NSR609Bs for 55nm and 610Cs for <50nm NAND at Toshiba, and multiple ASML 1700is at Samsung for ~50nm chips. Solutions for the few remaining difficulties are at hand, and machines designed to achieve the maximum resolution possible with water as the immersion fluid are being delivered in time for the 45nm chip generation.
However, 45nm may be the high-water mark; the course beyond that seems murky. Exposure wavelength will remain fixed at 193nm, so media with higher refractive indices are needed if dimensions are to shrink in single-exposure lithography. Synthetic (Generation-2) immersion fluids with indices around 1.64 (14% higher than water) have appeared, but development of suitable lens materials is delayed. Worse, the ~10% resolution improvement possible with Gen-2 immersion is insufficient for 32nm production, for which the immersion fluid, lens material, and resist must all have an index of refraction near 2.0.
Thus, symposium chairman Bryan Rice, Intel assignee to SEMATECH, visualizes an insertion point for high-index (Hi-n) immersion at the 22nm node with double patterning, giving the crystal growers and resist chemists more time for R&D. Roger French of Dupont claimed that Gen-2 technology could improve the production economics even for cases like 22nm double patterning, where water immersion seems theoretically feasible. The question is whether that improvement will be enough, or whether some other development-like EUV-might make high-index immersion irrelevant by the time it is ready for production. A decision on Gen-2 exposure tool development is coming early next year, according to Diane McCafferty of ASML.
The properties of plausible lens materials must be understood before any such decision is made-and it is particularly disappointing that the absorption of the favorite Hi-n material, LuAG (lutetium aluminum garnet, n = 2.15), remains twice the target needed to demonstrate feasibility, and >20× that possible for a production system. The problem, according to Lutz Parthier of Schott Glass, is obtaining consistently pure starting material. Schott says it has grown an 80mm × 300mm boule of LuAG using a core-free process that keeps the index uniform, with attenuation (0.11cm-1) sufficient for laser damage studies and interferometric lithography experiments. Prisms for interferometers and samples for test will be fabricated by year’s end, Parthier reported, with the goal to produce the first 150mm-dia. lens blank before the end of 2009.
The alternative lens crystal is BaLiF3, being developed by Tokuyama Corp. in Japan, with a lower index (n = 1.64) that makes it suitable for Gen-2 (though not Gen-3) systems. It is related to widely used materials such as CaF2. Growing uniform, strain-free, low attenuation crystals of BaLiF3 has proved challenging. Toshiro Mabuchi of Tokuyama reported in a poster that 150mm-dia. single-crystal boules have been grown and annealed to push attenuation below 0.003cm-1 and stress birefringence below 1.7nm/cm. Laser durability and homogeneity tests are underway, with a final assessment planned for mid-2008.
Organic Hi-n fluids have higher viscosity and lower surface tension than water, restricting the scan speed of current local-fill immersion technology. Alternatives include a wafer-wet design or a scheme where droplets left behind during the exposure scan are mopped up later. Both require that the fluid and resist do not interact over fairly long time periods, reported ASML’s McCafferty . Taiichi Furukawa of JSR reported that low-attenuation Gen-2 fluids had been synthesized and specially developed topcoats resulted in contact angles above 70°, potentially speeding throughput. Technologies to purify and de-gas the expensive Gen-2 fluids for re-use had been shown to work, according to several authors.
Gen-3 fluid, however, is another matter. Chemical schemes to increase the index of refraction of liquids had not given high enough indices or low enough attenuations at 193nm. So, the plan had become to suspend nanoparticles of high-index solids (like LuAG) in the immersion fluid. John Hoffnagle of IBM derived an inequality that showed that the nanoparticle dimensions have to be as small as a single molecule if 10% of the light is not to be scattered, or the “fluid” will congeal into moist nanoparticle sand.
A panel discussion on Hi-n materials agreed that cost and timing were key concerns. Will Conley of Freescale Semiconductor and Harry Sewell of ASML both advocated increased R&D funding to make materials available when they will be needed. One problem is that the organizations capable of such advanced research were terribly burned in the 157nm lithography debacle, and are wary of the financial dangers of such speculative large-scale projects. Another is the timing: L.J. Chen of TSMC pointed out that his company would need an exposure tool in 2009 for 22nm process development. A Gen-3 (NA = 1.85) prototype would support single exposure technology with k1=0.31-otherwise, double patterning would be adopted. The state of Hi-n technology reported at this symposium suggests a tremendous flood of innovation will be needed. -M.D.L.
The wonders of water
The sessions on water immersion technology seemed to wash away the murk of the Hi-n problems, though perhaps in a surge of hype. Jos Beschop of ASML claimed that >3M wafers had been processed by his firm’s immersion systems, and that the ASML XT:1900i is production-ready with CD uniformity of 1.5nm for 45nm linear structures and overlay at the 4nm level. Andrew Hazelton of Nikon reported that 10 NSR-610C systems have been shipped, capable of 40nm line/space patterns. Since the auto-focus sensor was calibrated during every wafer change, the focus accuracy was 15nm. Over a two-month period, Nikon’s local fill technology had maintained a defect level of 0.07cm-1, he noted. Canon, meanwhile, reported the status of its yet-to-be-delivered FPA-7000-AS7 water immersion tool, claiming even lower defectivity due to an innovative cleaning process from TOK.
Defects due to water droplets and bubbles have been conquered, according to the speakers, but those related to particles need continued attention. Many wash onto the wafer from the edge bevel, where topcoat materials tended to delaminate. Eliminating the spun-on topcoat material by adding a material to the resist that segregated to the surface produced the best results, according to Kentaro Goto of JSR. The receding contact angle for that in situ topcoat was 86°, higher than most spun-on materials. He also reported that a new rinse step eliminated the “blob” defect that appears on unexposed resist.
Katsushi Nakano of Nikon reported that a new optimized edge process from TEL insures that the topcoat does not extend beyond the BARC layer, reducing particles by a factor of two in volume production. Jan Willem Cromwijk of ASML reported that 28 1700i systems in high-volume production maintain a 10 defect/wafer level for three months. Keeping the tool running during idle time with special “autoflush” wafers reduced defects by 80%, and proper edge treatment and bevel cleaning reduced the remainder by 60%. However, the more sensitive metrology used for first five XT:1900i tools revealed 37 defects/wafer, he admitted.
Focus sensor technology was one subject of controversy on early immersion tool designs. ASML’s Twinscan system allowed the wafer height mapping technology of their dry tools to be applied in immersion. Nikon implemented a new water immersion wafer mapping scheme on the lens. After some engineering effort, both appeared to work. However, Li-Jui Chen of TSMC reported a peculiar anomaly characteristic of ASML’s 1400i and 1700i scanners-the wafer heights measured dry did not predict proper focus accurately enough across the immersed wafer. Evidently the weight of the water and the uneven cooling introduced across-wafer variations of up to 89nm for the 1400is-and worse, the shift depended on many things, including scan speed, contact angle, and field size. While special procedures reduced the uncorrected variability to 40nm on the 1700is, the final solution was a new ceramic wafer table material on the 1900i with better stiffness and thermal characteristics, reducing the systematic variation to 15nm. K.S. Chen reported that TSMC’s 1400i immersion tools are being converted to back dry lithography, but that 45nm production would begin there on 1700i tools by year’s end. -M.D.L.