Industry confronts porous dielectrics...again
12/01/2007
EXECUTIVE OVERVIEW
The semiconductor industry’s last attempt to integrate porous dielectrics ended in a retreat to simpler solutions. This time, none of the choices are simple. Either porous dielectrics or, even more radical, air-filled cavities are needed to keep circuit performance on track as copper resistance rises.
We’ve been here before. Once again, the semiconductor industry is struggling to determine the best integration scheme for porous dielectric materials. Back in the late 1990s, industry analysts debated the relative virtues of copper and low dielectric constant (k) materials, confidently predicting that low-k dielectrics, including porous materials, would appear in manufacturing first.
That idea collapsed, literally, once people started trying to package chips with the available low-k materials. While the Young’s modulus of SiO2 is about 70GPa, porous dielectrics offer a modulus of 5GPa or less [1]. Once manufacturers confronted the problems of CMP damage, etch damage, and moisture uptake, porous dielectrics were abandoned in favor of simpler solutions, such as the carbon-doped oxide and copper metal combination that now dominates.
Yet today’s engineers really have no choice but to ignore history and take another look at porous dielectric integration. The last time around, copper interconnects were able to shoulder the burden of performance improvement. By replacing aluminum with copper and adding metal layers, designers were able to work around the relatively moderate reduction in capacitance that carbon-doped oxides provide. Although carbon-doped oxides have demonstrated steady improvement in the intervening years, copper itself has begun to reach its practical limits.
Lots of work, and advantages
In particular, the resistivity of copper increases sharply as linewidth drops below 100nm (as discussed in Part 1 of this series, “Interconnect: Future nodes look beyond copper,” Oct. 2007, p. 28). Very thin barrier layers are needed to minimize size effects, but achieving a thin, pinhole-free, conformal barrier coating has been difficult. Reducing the dielectric constant allows manufacturers to relax their resistance specification and still achieve the desired performance. Simulations by STMicroelectronics showed that at the 32nm node, achieving the RC specification with a bulk dielectric constant of 2.5 requires a 25% reduction in circuit resistance. Reducing the bulk dielectric constant only slightly, to 2.3, gives 5% less circuit capacitance and means that only a 20% reduction in resistance is necessary. Adding a low-k etch stop layer, such as SiCN with a dielectric constant of 4, gives a 10% improvement in capacitance and eases the resistance requirement to a 15% reduction [2].
Reducing the dielectric constant is especially useful for local interconnects, where wires are shorter and have smaller cross-sections. These wires, being smaller, will encounter size-related resistance effects before the rest of the interconnect structure. At the same time, the STMicroelectronics simulations found that in shorter wires, intermetal dielectric capacitance can account for as much as two-thirds of the total delay.
The good news is that manufacturers have learned a lot about dielectric integration since low-k materials first appeared on industry roadmaps, explained Applied Materials managing director of dielectrics, Derek Witty. Low downforce CMP is now routine, for instance, addressing one of the key mechanical challenges for weaker materials. At the same time, improvements to etch stop and dielectric barrier layers have reduced their dielectric constants, helping manufacturers achieve a lower integrated k value with a higher bulk dielectric constant.
Making pores
Still, the introduction of porosity changes the game again. Porous dielectric integration schemes are complicated both by the need to generate the pores in the first place, and the need to protect the material during further processing. One of the most-discussed approaches co-deposits the carbon-doped oxide matrix material with a poragen. A curing step, assisted by UV light, an electron beam, or laser annealing, drives off the poragen and crosslinks the matrix structure for maximum strength. Especially in highly porous films, curing can cause shrinkage of 10-15% or more. The films have not yet been patterned when the cure takes place; though some shrinkage is acceptable, it can also degrade adhesion to the underlying layer.
The next step, patterning, poses the most severe risk of film damage. Outgassing of poragen byproducts can poison the resist, while extended etch and strip processes increase the risk of film damage. One solution, the trench-first hard mask approach, places a thin masking layer between the dielectric and the resist, so that the resist never comes in contact with the dielectric. Because the masking layer is relatively thin, patterning requires only a thin resist layer and a correspondingly brief resist strip. This approach does, however, add a number of additional process steps. For any integration scheme, the situation is likely to become even more challenging as the need for continuous improvement demands steady increases in film porosity. A k value of 2.5 can be achieved with only 25% porosity, Witty said, but the 32nm node requires k values between 2.1 and 2.2, probably requiring 35% porosity. Dielectric constants below 2.0 will probably require >50% porosity, according to ASM International CTO Ivo Raaijmakers.
Open pores threaten the integrity of the metal-dielectric interface, as they can allow contamination and penetration by barrier precursors. The roughness of the resulting barrier can either degrade the quality of the subsequent copper deposition or allow copper to penetrate into the material. Some sort of pore sealing treatment will be required for the 32nm and smaller technology nodes.
The search for pore sealing treatments has focused on the resist strip step. Etch and strip leave the dielectric, and especially the feature sidewalls, exposed to contamination. A strip process that simultaneously passivated the dielectric surface would minimize the window for damage. Oxygen plasma leaches carbon out of carbon-doped oxides, so instead manufacturers are looking at such chemistries as CH4, NH3, or He/H2 ions. Of these, Mohamed Aimadeddine and coworkers at STMicroelectronics found that CH4 is probably the most promising [3]. In their study, an He/H2 strip failed to prevent precursor diffusion. Both CH4 and NH3 prevented diffusion of both Ti and Ta. However, NH3 depleted carbon from the dielectric surface, making it hydrophilic and vulnerable to moisture uptake. CH4 increased surface carbon, preserving the hydrophobic character of the surface and minimizing moisture uptake.
 Air gap integration process sequence [4]. |
Unfortunately, no solution is perfect. CH4 also raised the integrated dielectric constant to 2.7, from 2.5 for an untreated reference sample. Materials with lower dielectric constants and more porosity are likely to require more extensive surface modification. It is not yet clear whether CH4 will provide adequate sealing with acceptable dielectric performance.
A more aggressive but less attractive approach to pore sealing inserts a dense dielectric liner between the porous dielectric and the metal barrier. Besides raising the dielectric constant of the stack, this layer affects the relative thicknesses of the metal and dielectric features. If designers hold metal width constant, then the liner increases the capacitance, offsetting the advantage provided by the porous bulk dielectric. If, on the other hand, designers hold the dielectric width constant, the metal width-already a critical parameter due to size effects-decreases. Still, liners provide the most effective possible protection for porous dielectrics. They may also be needed for mechanical support.
In order to minimize the mechanical impact of porous dielectrics, some schemes use these materials in only the most critical areas, while continuing to use either SiO2 or a dense carbon-doped oxide wherever possible. These hybrid schemes aim to balance performance against integration complexity and structural robustness.
Yet the more complex the dielectric integration scheme becomes, the less performance benefit it offers. When confronted by an additional set of process steps for liner deposition, or the complications of a hybrid integration scheme, manufacturers may decide that the benefits simply don’t justify the costs.
One alternative to porous dielectrics might be to introduce air gaps into the interconnect structure. Air, after all, has a dielectric constant of 1.0, far lower than any likely porous materials. Though air gaps would inevitably require the addition of dielectric support structures, these could have relatively high dielectric constants and still lead to a good overall capacitance. Everyone interviewed for this article agreed that the possibility demands further investigation, especially for the 22nm and smaller technology nodes. Greg Smith, a senior member of Sematech’s technical staff, even suggested that a few early adopters might introduce air gaps at the 32nm technology node. The figure shows an air gap integration process sequence [4].
Making room for air
One of the simplest schemes for introducing air into the dielectric structure takes advantage of the nonconformal behavior of PECVD deposition. After metal deposition and CMP, a second oxide etch cuts wells into the oxide layer. Then, nonconformal CVD deposits a blanket layer for the next dielectric. This deposition gradually pinches off the tops of the pre-etched wells, trapping voids inside.
Though simple to describe, this scheme is difficult to implement. For example, it’s not possible to simply etch all of the intermetal spaces away, leaving only the barrier layers and dielectric liners. Even if such a design were structurally rigid enough, unlanded vias on the next level could punch through into a void, creating a serious reliability problem. Instead, manufacturers must restrict void placement to regions far enough away from vias, using an additional lithography step.
To address concerns about unlanded vias, manufacturers are considering a variety of sacrificial materials for use in air gap schemes instead. These schemes use the sacrificial material in a hybrid scheme with a permanent dielectric that will remain behind after processing. For example, one proposed scheme uses porous SiLK for via layers, with SiO2 for the intermetal dielectric. Immersing the structure in HF dissolves the SiO2. The porous dielectric remains behind; the pores allow diffusion of the HF to the areas to be removed. Another alternative uses a thermally degradable layer as the sacrificial material.
Use of a sacrificial layer gives manufacturers control over the placement of air gap regions. For instance, it might be desirable to place a dense dielectric under bond pads, while air gaps might help improve the performance of the most critical areas of the chip.
So far, most implementations of sacrificial air gaps have focused on test structures with only a few layers. Though results are promising, important yield questions remain. If the sacrificial material thermally degrades, what happens to the degradation byproducts? Can outgassing lead to the kind of “popcorn” cracking that can afflict plastic packages? If the sacrificial material is SiO2, can the HF etch fully penetrate and escape from the desired structures?
During processing, the dielectric liner helps protect the metal barriers from damage during the HF etch. Once the chip reaches customers, the liner is crucial for reliability. Copper electromigration causes failures when the metal breaks through a crack between the top and sidewall barrier layers. To resist this force, the barrier layers need a strong interface with the dielectric. In air gap schemes, the dielectric liner must be strong enough to resist electromigration without mechanical support from the bulk material.
Both air gaps and porous dielectrics present substantial risks and uncertainties. No one really knows whether a ten-level interconnect stack will collapse if its foundations rest on such materials. No one knows whether dielectric liners and metal barriers can contain the electromigration of copper. It would be nice to have another alternative, either another approach or a way to design chips to minimize the importance of the intermetal dielectric.
Can 3D integration redesign the problem?
One possibility, 3D integration, has been used primarily to reduce system form factor by stacking dice vertically instead of placing them adjacent to each other. Space-oriented designs stack chips on top of each other, but connect them with wirebonds. A performance-oriented chip stacking approach might use through-silicon vias, providing large copper “nails” for fast, low-resistance interconnects between vertically stacked dice.
In principle, such an approach is relatively simple. However, as Raaijmakers explained, it depends on several new technologies. High speed, high aspect ratio etching is needed to cut the vias, and high aspect ratio copper deposition to fill them. Alignment accuracy between layers will become more important over time, as circuit density increases. As in other multichip packages, each chip must be tested before integration, and the integration scheme may not introduce additional defects. Still, the process challenges of 3D integration do not appear to present a significant obstacle, at least compared to porous dielectrics or air gaps. Instead, many of the challenges for through-silicon vias are on the design side. To capture the maximum performance benefit, designers would need to think about the best ways to partition systems within a stack. To minimize resistance, critical paths should be relatively short, but close packing of critical components can increase heat dissipation issues.
In the end, 3D integration does not solve the circuit capacitance problem. Individual high performance components will still need to minimize interconnect delay, whether or not they are incorporated into a stacked package. In the end, rather than avoiding the question, manufacturers may finally have to find an answer for porous dielectric integration.
References
- Willi Volksen, et al., “Laser Spike Annealing: A Novel Post-Porosity Treatment for Significant Toughening of Low-k Organosilicates,” IEEE Interconnect Tech. Conf., pp. 146-148, 2006.
- M. Aimadeddine, et al., “Robust Integration of an ULK SiOCH Dielectric (k = 2.3) for High-performance 32nm-node BEOL,” IITC 2007, pp. 175-177.
- M. Aimadeddine, et al., “Effect of CH4 Plasma on Porous Dielectric Modification & Pore Sealing for Advanced Interconnect Technology Nodes,” IEEE Interconnect Tech. Conf., pp. 81-83, 2006.
- T. Harada, et al., “Extremely Low-keff (1.9) Cu Interconnects with Air Gap Formed Using SiOC,” IEEE Interconnect Tech. Conf., pp. 141-143, 2007.
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Katherine Derbyshire is a contributing editor at Solid State Technology. She received her engineering degrees from the Massachusetts Institute of Technology and the U. of California, Santa Barbara. She is the founder of consulting firm Thin Film Manufacturing, PO Box 82441, Kenmore, WA 98028 United States; e-mail [email protected], www.thinfilmmfg.com.