Manufacturing integration considerations of through-silicon via etching
12/01/2007
EXECUTIVE OVERVIEW
Through-silicon vias (TSV) will provide interconnect capability among multiple die in advanced three-dimensional integrated circuit (3D IC) designs. TSVs differ from the vias currently used in multilayer interconnects primarily in their size (1-100µm dia. and 10-400µm depth) and their need to penetrate not only the various materials that compose the overlying circuitry but also the significant depth of the silicon substrate. Manufacturers are currently considering a wide variety of 3D integration schemes, with an equally broad range of TSV requirements. Plasma etch technology, which has been used extensively for deep silicon etching in memory and MEMS production, is well suited for TSV creation.
The market forces driving 3D IC development include consumer demand for greater functionality in smaller devices, enhanced performance in advanced computing systems and, ultimately, lower cost. Thinned chips connected by TSVs can reduce the form factor (height and width of the packaged chip stack) relative to current wire bonding technologies. While form factor has led the initial wave of TSV implementation, performance benefits appear to be a significant driver for 3D IC designs. This will continue as multicore microprocessors evolve; the need for TSV stacked memory will grow substantially (Fig. 1).
 Figure 1. Trends in 3D IC TSV relating various applications to increasing vertical I/O density and decreasing wafer thickness and via CD. |
3D integration may simply be less expensive in the long run compared to continued shrinking of planar circuitry. The cost of implementing each successively smaller generation of planar CMOS is growing at an alarming rate. Thus industry innovators look at alternative approaches, such as extending the integration of circuits into the third dimension. Still, major challenges for 3D IC development exist in design, manufacturing, and test. Manufacturing aspects of the TSV include via formation, metallization, wafer thinning, alignment, and bonding. We focus here on the challenges and potential solutions for TSV formation using plasma etch processes for high-volume production.
3D TSV integration: via-first and via-last
Each 3D IC application imposes different requirements on the integration design and its process implementation. Not only do TSVs vary widely in size and the materials they pass through, they may be created at various points in the manufacturing sequence-in the frontend wafer fab (before or after FEOL processes), or in the assembly and packaging facility (before or after bonding). When viewed this way, the integration schemes under consideration can be classified as via-first or via-last, depending on when the vias are created.
 Figure 2. Various through-silicon via (TSV) integration schemes can be classified by when the vias are created in the manufacturing process. |
Figure 2 shows cross-sectional schematics of the four basic approaches to TSV formation. Via-first integration forms the TSVs in the wafer fab during frontend processing, and the vias are generally smaller, ranging from 1-10µm dia. and 10-60µm in depth. Via-first integration is further subdivided into processes that occur before transistor formation and those that occur after transistor formation but before local interconnect. Via-last integration takes place in assembly and packaging after wafer processing is completed and typically creates fewer, larger vias, 20-50µm in dia. and 50-400µm deep. Via-last integration can be divided into processes that occur before or after bonding, either to a carrier substrate or another device wafer.
 Figure 3. Summary of TSV etch requirements for various integration approaches. |
Figure 3 summarizes the etch requirements for various integration schemes. The materials etched may be silicon only or may also include the full list of metals and dielectrics used for local interconnects, passivation, and even bonding. The mask may be photoresist (PR) or a silicon dioxide hard mask (HM). Via diameters and depths range widely, but aspect ratios are almost always greater than 3:1 and may exceed 10:1. In most cases, the vias are etched blind into the substrate, then revealed by thinning, though some via-last processes etch to a stop layer. Many of the schemes require some means to prevent damage to silicon exposed near the wafer edge.
Via-first before FEOL. Vias are relatively small, 2-5µm CD and 30-50 µm depth, with higher aspect ratios as they are used for higher density interconnects (Fig. 4). Used for advanced integration, there may be many thousands of vias per die, packed in closely spaced local arrays. Photoresist is the preferred mask material since it minimizes the number of process steps and is easily stripped in situ, but hard masks may also be used. In most cases, a modified Bosch etch process is used.
Precise profile control (taper, tilt and sidewall roughness) is essential to ensure the quality of subsequent layer deposition and fill processes. This, combined with the exacting requirements for maintaining via depth, presents a significant challenge to maintaining etch uniformity across the wafer, particularly for 300mm wafers. The similarity between SEMs acquired near the edge (Fig. 4) and near the center (Fig. 5) of wafers demonstrates that excellent cross-wafer uniformity can be achieved. Repeatability and predictability require careful attention to chamber cleanliness to prevent the build up of process materials that can affect etch performance (process drift and particle defects).
Via-first after FEOL. Vias are typically somewhat larger, 5-20µm CDs and 40-150µm depths. Etch challenges are similar to via-first before FEOL integration, but this approach requires first opening of the dielectric layers that were part of the FEOL fabrication with more conventional dielectric etch processes. During the deep silicon etch, additional emphasis must be placed on controlling undercut to facilitate the subsequent metallization processes.
The most significant process decision is the choice between a steady state process or Bosch process for the deep silicon etch. Steady state processes are sufficient for low aspect ratio vias and when some erosion of the pre-metal dielectric (PMD) layer can be tolerated. Bosch processes are better for deep, high aspect ratio vias that require high selectivity and tight tolerances. Photoresist is preferred to eliminate PMD erosion and protect devices and delicate gate structures that have already been formed. Ideally, the same photoresist mask can be used for etching both the dielectric layer and deep silicon.
Via-last before bonding. These processes use thick photoresist and create the largest vias, with 20-50µm CDs and 50-400µm depths. The interconnect density is usually lower, on the order of a hundred TSVs per die. Processing in the frontend wafer fab is complete, and the vias must penetrate the full stack of BEOL insulators and conductors in addition to the silicon substrate (Fig. 6). Conventional steady state processes for conductor and dielectric etching are used to go through the BEOL stack.
If metal layers such as aluminum are to be etched, passivation to control corrosion should be used in a separate stripping process prior to the wafer being re-exposed to atmosphere. While surface roughness must be minimized, integration schemes for these larger structures are more tolerant compared to via-first applications. Because these are the deepest silicon etches, special attention must be given to prevention of undercut of the BEOL dielectrics. For this reason, a Bosch process is usually employed for the deep silicon etch portion.
Via-last after bonding. Vias created after bonding are typically not as large as via-last before bonding, but larger than via-first, with 5-50µm CDs and 30-150µm depths. The interconnect density may be on the order of a hundred per die or higher. Unlike most other integration schemes in which the via is etched “blind” to a specified depth from the device side, processes that create vias after bonding usually are etched from the backside of a wafer that has already been thinned.
In this scheme, the vias are etched to a stop layer, typically the first dielectric layer of the FEOL device. While this reduces the etch rate uniformity requirement somewhat, one must modify the process to prevent notching of the silicon at the stop layer interface. For features with similar dimensions and low aspect ratio, this can be accomplished with highly passivating chemistries that cause tapering near the interface. Use of pulsed RF bias during the etch, a technique traditionally applied in MEMS, can also be used to eliminate this phenomena. One disadvantage of this scheme is that an additional, separate etch step is required after the isolation dielectric deposition to allow contact to buried metal sites.
Plasma etch technology for TSVs
Plasma etching is an ion-enhanced chemical process, thus often referred to as reactive ion etching (RIE). Etch systems use RF powered plasma sources for the creation of ions and chemically reactive species. In deep silicon etching, the primary source gas used is sulfur hexafluoride (SF6), which supplies highly reactive free fluorine for high etch rates in silicon. Ions in the plasma are accelerated toward the wafer with strong directionality by a potential difference (RF bias) between the plasma and the wafer (the electrode on which the wafer is placed). While this gives rise to enhanced removal rate in the vertical direction, additive chemistry for passivating the etched sidewalls is required for highly anisotropic profile evolution.
There are two ways to provide sidewall passivation for deep silicon etching; the first is the conventional approach in which additive gases such as O2 and/or HBr are mixed with SF6. These steady state processes have limited capabilities in terms of selectivity to photoresist and usually require a hard mask, such as silicon dioxide. The second approach is the so-called Bosch process, which uses rapid alternating steps of etching with an SF6 plasma and deposition with a polymerizing gas such as C4F8. Because of the polymer deposition and low RF bias voltages, this process has high selectivity to photoresist and in some cases can exceed 100:1.
Profile control
The details of the TSV manufacturing process depend upon the various integration options. In addition to via size and shape, considerations include which materials the vias must penetrate and the avoidance of plasma damage. Generally, different materials require different etch chemistries and different plasma conditions. Vias that pass through different materials can be created by moving the wafer between chambers with different chemistries and often different designs (integrated processing) or by changing the chemistry within a single chamber (in situ processing).
The key benefits of in situ processing are reduced capital investment (fewer chamber types), decreased floor space, shorter cycle time through the manufacturing sequence and higher overall throughput. The system needs a higher number of process gas options for each chamber, for example, chlorinated gases for certain metal etches, fluorocarbon gases for dielectric etching, SF6 and C4F8 for deep silicon etching, and common additive gases such as argon, oxygen, nitrogen, and helium. Due to the rapid gas switching requirements of the Bosch process, the gas box must be situated in close proximity to the process chamber, making the system integration more intricate.
Integration flexibility means that the reactor must be designed for the Bosch process as well as conventional etches. High density plasma (HDP) sources are the typical reactors used for the Bosch process and have been used for etching a wide range of semiconductor materials. HDP systems employing ICP, or Transformer Coupled Plasma technologies, have highly independent means for controlling bias voltage, which determines the energy of ions bombarding the surface. The ability to control power and bias independently permits the process to be tuned for optimal performance for a wide range of applications.
Profile control includes all aspects of shape, including depth, undercut, taper, smoothness, tilt, and cross-wafer uniformity. Controlling these various aspects at high silicon etch rates requires a system that has a wide process window in terms of operating conditions. Because most plasma etch reactors are radially symmetric, non-uniformity typically appears as a variation in etch rate, profile shape, or profile tilt between the wafer center and edge. Narrow, high aspect ratio features are most difficult to control in terms of profile characteristics. Nonetheless, with proper system design and process development, highly acceptable profiles can be fabricated (Fig. 5).
Subsequent processes for providing a thin dielectric liner and metallization impose certain requirements on the profile shape. While plasma enhanced CVD used for depositing oxide can be conformal, PVD processes for barrier or seed layers have difficulty forming continuous layers over a significant undercut of the silicon to the overlying films. Metallization for filling the via using CVD tungsten or electroplated copper are common, often favoring a tapered profile. Processes with minimal undercut and tapered profile can be afforded with some tradeoffs, depending on the extent of the requirements. For example, tapering of a via can be accomplished by increasing sidewall passivation, which tends to slow down both the lateral and vertical etch rates.
Conclusion
The wide variety of integration schemes under consideration for 3D ICs brings an equally wide range of requirements for TSV. High-volume production requirements for repeatability, reliability, and throughput at the lowest possible cost of ownership must be met. Plasma etch has the needed flexibility and a proven record for deep silicon etch in MEMS and memory device applications. For TSV applications, the essential attributes include fast, precise, independent manipulation of physical, electrical, and chemical parameters; process uniformity across 300mm wafers; in situ processing for multiple film stacks; and Bosch process capability for high aspect ratio via etching through silicon.
Acknowledgments
Syndion is a trademark of Lam Research Corp. Transformer Coupled Plasma is a trademark and patented process of Lam Research Corp. The author would like to acknowledge the Lam Research Corp. 3D IC etch team and, specifically, Robert Chebi, Frank Lin, Wan-Lin Chen, and Jerry Winniczek for the work presented in this article.
Steve Lassig received his BS and MS in materials engineering from Rensselaer Polytechnic Institute. He has worked in the IC industry for more than 25 years and has more than 30 technical publications and numerous patents. He is senior product marketing manager for the 3D IC etch product line at Lam Research Corp., 4300 Cushing Parkway, Fremont, CA, 94538 United States; ph 510/572-0200, e-mail [email protected].