DRIE from MEMS to wafer-level packaging
12/01/2007
EXECUTIVE OVERVIEW
Deep reactive ion etching (DRIE) has enabled the manufacturing of many different types of MEMS devices. The technique is now starting to be applied to the formation of through-silicon vias (TSVs) for electrical interconnects between stacked die in advanced 3D-IC applications. Recent developments to plasma etch tools now allow etch depth uniformity and etch direction to be accurately controlled on wafer sizes up to 300mm.
DRIE of silicon, utilizing alternating steps of etch and passivation of a feature, was devised at Robert Bosch GmbH [1]. The inventors, Laermer and Urban, were recently awarded the title of European Inventor of the Year by the European Patent Forum, recognizing the significant impact that the technology has had on the successful commercialization of micromachines or MEMS.
The production of early manufactured MEMS devices-pressure sensors, accelerometers, and miniature gyroscopes-was driven by the automobile industry, but following soon afterward came new applications in optical systems. These included actuated micro-mirror switching systems for directing optical transmissions from input fiber optics to chosen fiber optic output paths, and the very successful digital light processing (DLP) chips for video projection systems in industry and the home. Fluid transfer and mixing systems have been realized on the micro scale and the application of DRIE to the manufacturing of parts of printer ink jet heads is a rapidly growing, perhaps one might say, maturing, market. In the biomedical field, lab-on-a-chip is becoming a reality in addition to other applications, such as microneedles, implantable sensors, and surgical tools.
DRIE has now begun to excite much interest as a method of creating through-wafer vias (TWVs) in advanced 3D-IC and other packaging applications.
DRIE for through-wafer interconnects
3D vertical interconnects can be etched using DRIE as an alternative to wire bonding in SiP, SoC, and 3D-IC applications. Via holes must be etched through the wafer/stack and then metallized in order to form interlayer contacts. Interconnect trends in the semiconductor industry have been lower power consumption, reduced form factor, and increased integration. At ECTC2006, Intel presented a paper that stated while Cu/low-k interconnects remain the most attractive interconnect option into the foreseeable future in terms of scaling, 3D vertical interconnections probably offer the most interesting and realistic option for the near future for semiglobal and global interconnects meeting technology trends [2].
 Figure 1. Schematic diagram of the Faraday cage arrangement used to suppress cross-talk. (Courtesy of MIT) |
Another use of TWVs was illustrated by researchers at the Massachusetts Institute of Technology (MIT), who fabricated a “Faraday cage” structure (Fig. 1) to suppress substrate cross-talk in system-on-chip applications [3]. They used DRIE processing to etch a ring of high aspect ratio vias (lined with SiN and filled with copper) around a noisy or sensitive device in the chip.
 Figure 2. Integration of through-wafer copper interconnections and solder bumps. (Courtesy of National Tsing Hua U.) |
In Taiwan, researchers from National Tsing Hua University have used DRIE processing to fabricate vias through a 550μm thick silicon wafer, using an aluminum hard mask, and infilled with thermal oxide and electroplated copper. MEMS microtemperature sensors were fabricated on the frontside of the wafer and solder bumps were then directly electroformed (using photoresist molds) onto the copper interconnections [4] (Fig. 2).
Time-multiplexed etch processing
The time-multiplexed etch process developed by Laermer and associates at Robert Bosch enables the highly anisotropic etching required for many MEMS applications. Surface Technology Systems was the first process tool manufacturer to take a license for this “Bosch Process” and over a period of more than 10 years has further developed it into the advanced silicon etch (ASE) process [5-7].
The ASE process works by the use of repeated cycles of passivation and etch. In each passivation step, a precursor gas is subjected to the plasma, which results in a polymer layer being deposited on all surfaces of the features being etched. In the first part of the following etch step, ions accelerated toward the wafer preferentially remove the polymer from the base of features. In the remainder of the etch step, neutral fluorine radicals react with the exposed silicon at the base of the features, isotropically etching the material.
The next passivation step then causes polymer to be deposited on all surfaces of the features including the silicon exposed during the previous etch step. As the cycles of etch and passivation repeat, the features are etched ever deeper into the silicon. The etching of the silicon is overall highly anisotropic, but in each cycle, the etch process is essentially isotropic. It is possible to achieve very high aspect ratios to features using this process, >50:1 in some cases, with good average CD control and high selectivity of order 200:1 to the mask. However, the sidewalls of the features may exhibit a roughness described as “scalloping” due to the isotropic etch part of each cycle. For applications requiring low sidewall roughness (such as optical devices), etch rate would normally need to be reduced. However, by careful design of the process tool, it is possible to reduce the length of the cycle time while maintaining etch rate to near constant.
Etch process considerations
Plasma process equipment designed to operate the ASE process uses the inductive coupling of RF power (ICP) into the plasma using an antenna that is usually situated on the atmospheric side of a dielectric window that forms part of the plasma source region. ICP plasma processing equipment may be configured so that the plasma is formed in the same chamber in which the wafer is processed. Alternatively, the plasma may be formed in a separate chamber (de-coupled plasma source) and allowed to diffuse into a second usually larger chamber in which the wafer is located.
The use of a de-coupled plasma source brings a number of benefits:
- The reduced volume of the source allows more efficient breakdown of the precursor gas because of the higher power density that can be delivered from the RF power supply.
- The geometry and volume of the source region can be tailored so that the ions and neutral radicals exiting it can diffuse down to the wafer with the desired profiles to obtain high etch uniformity.
- Additional means may be included between the de-coupled plasma source region and the process chamber in order to alter the balance between numbers of ions and numbers of neutral radicals reaching the wafer to control selectivity to mask and/or ion damage to feature profiles.
For a conventional de-coupled plasma processing tool, ions and radicals diffuse from the smaller chamber into the process chamber. Due to the differences in deflection or loss probability between ions, electrons and neutral radicals when encountering electric or magnetic fields and material surfaces such as the chamber walls, the radial profiles of the charged species may differ from the radial profiles of the neutral radicals in the vicinity of the wafer.
For the conventional de-coupled plasma processing tool, the spatial profile of both ions and neutral radicals in the vicinity of the wafer will usually be center high, decreasing radially towards the walls of the chamber. The density profile variation of the ions will usually be more extreme than for the radicals, because on encountering the walls or an object within the chamber, ion and electron pairs have a high probability of recombining, while neutral radicals may survive a few interactions. For chemical etching of silicon with a reasonable exposed area (exposed silicon area on the wafer surface defined by the mask), to achieve a near constant chemical etch rate across the wafer, more radicals are required near the center where each feature is surrounded by other features, than towards the edge. The conventional de-coupled plasma processing tool can often quite reasonably satisfy this criterion.
Because the ion density profile above the wafer is center high, the Debye length and therefore the thickness of the sheath between the plasma and the wafer will be less near the center of the wafer than towards the edge. This non-uniformity of the sheath thickness across the wafer is likely to lead to a steering of ions as they are accelerated to the wafer. In the center of the wafer, the ions will move perpendicular to the wafer surface, but towards the edge of the wafer they may move in such a way that they impact the wafer at an angle to the perpendicular. In this way, features may be etched perpendicular to the wafer surface near the center of the wafer, but at a significant angle to the vertical near the edge of the wafer, with the feature tilting outwards (from wafer center) as it is etched deeper into the wafer. The deeper the etch, the more pronounced the effect.
An ideal plasma processing tool should have the capability of delivering neutral radicals to the wafer surface with a density profile to match the loading effect of the exposed area of silicon so that the etch rate is very close to constant at all points on the wafer. The tool should also be capable of providing a near uniform ion density just above the wafer surface so that the sheath is of the same thickness across the wafer and ions are accelerated perpendicular to the wafer surface.
DRIE for 300mm wafers
As the manufacturing of MEMS devices has moved from 150mm to 200mm wafers, it has become increasingly important to design plasma processing equipment that is capable of achieving deep, high aspect ratio features with very high etch uniformity over the larger wafer size and high etch rate to reduce the cost of ownership. For packaging applications, there is already a strong need for highly effective DRIE equipment suitable for TWV etching at the 200mm wafer size with the additional requirement in the immediate future of process equipment for 300mm wafers.
High etch rate and good uniformity of etch rate across the wafer are requirements for most users of plasma etch tools. Also, precise control of the etch direction so that it is very close to normal to the wafer surface at all points on the wafer is extremely important to maintain high yield of devices for deep etch applications, such as the manufacturing of MEMS accelerometers and etching of TWVs in 3D-IC applications.
Recently, STS developed a new plasma source intended for DRIE on 300mm wafers for such applications as TWVs in 3D-IC. In order to achieve high cross-wafer uniformity, techniques have been adopted that allow the radial profile of the neutral fluorine radicals that etch the silicon and the radial profile of the positive ions that drive the directionality of the etch to be separately adjusted. By ensuring that the ion density and sheath thickness are near constant across the wafer, the new plasma source can maintain close to vertical feature formation at all positions on a 300mm wafer and is equally capable of achieving this on 200mm and smaller wafers. Figure 3a illustrates the flexible control of tilt angle for a series of 200mm wafer trials in the new 300mm tool. Figure 3b shows the etch rate uniformity (<2.5%) achievable across a larger 300mm wafer.
 Figure 4. A 5µm wide slot etched >60µm deep using a 300mm DRIE source. |
Figure 4 is a SEM image of 5µm wide slot etched at 4.5µm/min into a 300mm wafer, exhibiting a slightly tapered vertical profile and acceptable levels of sidewall roughness for subsequent metallization.
Conclusion
DRIE is an enabling technology for device packaging applications in addition to MEMS. By careful design of the plasma processing tool, it is possible to obtain excellent etch uniformity across a 200mm diameter wafer, and more recently, 300mm wafers at high etch rate, while reducing to a low level the tilting of features towards the edge of the wafer. Etch rate/depth uniformity across the wafer is important for almost all applications of DRIE to achieve similar characteristics from die at any position on the wafer. Minimized feature tilting is desirable for many applications and essential to achieve high performance/yield for MEMS gyroscopes/accelerometers or maintain a through wafer via hole profile that is perpendicular to the wafer surface.
Acknowledgments
ASE is a registered trademark of Surface Technology Systems plc.
References
- F. Laermer, A. Schilp, “Method for Anisotropically Etching Silicon,” German patent DE4241045, 1992.
- M.W. Newman et al., “Fabrication and Electrical Characterization of 3D Interconnects,” Proc. of IEEE Electronic Components and Technology Conference 2006, p. 394.
- J.H. Wu, J. Schlovin, J.A. del Alamo, “A Through-wafer Interconnect in Silicon for RFICs,” IEEE Trans. on Electron Devices, Vol. 51, No. 11, Nov. 2004.
- C-J Lin, M-T Lin, S-P Wu, F-G Tseng, “High Density and Through-wafer Copper Interconnects and Solder Bumps for MEMS Wafer-level Packaging,” Jour. of Microsystem Technologies, Vol. 10, No. 6-7, Oct. 2004.
- J.K. Bhardwaj, H. Ashraf, “Advanced Silicon Etching Using High-density Plasmas,” Proc. SPIE, 2639, 224, 1995.
- J.K. Bhardwaj, H. Ashraf, “Anisotropic Dry Silicon Etching,” Symp. Microstructures and Microfabricated Systems at the Annual Meeting of the Electrochemical Society, Montreal, Canada, 1997.
- S.A. McAuley, H. Ashraf, L. Atabo, A. Chambers, S. Hall, J. Hopkins, G.J. Nicholls, “Silicon Micromachining Using a High-density Plasma Source,” Phys. D. Appl. Phys., 34, pp. 2769-2774, 2001.
Leslie M. Lea received his D.Phil and MSc in science and applications of electric plasmas from Oxford U., UK, and his BSc physics hons from Southampton U., UK. He is CTO and deputy CEO at Surface Technology Systems plc, Imperial Park, Newport NP10 8UJ, UK; ph 44/1633-652-455, e-mail [email protected].
Carolyn Short received her PhD in magnetic materials and her BEng in metallurgy from the U. of Birmingham, UK. She is a marketing communications engineer at Surface Technology Systems plc.