Technology news
11/01/2007
Doubling down at BACUS
Double patterning technology (DPT), self-aligned or not, seemed to be the consensus choice for the next half-pitch node or two for the maskmakers convened in Monterey for SPIE’s annual BACUS Symposium on Photomask Technology (Sept. 16-21). The evident delay in EUV technology poses special challenges for the photomask community and these were highlighted in a special Friday session, sub-titled: “Twice the pain for twice the gain.”
Artur Balasinski of Cypress Semiconductor began the session by reviewing the results from the SPIE panel held in February: Double exposure double etch (DEDE) methods (where the pattern of one resist film is developed and transferred before a second film is applied, etc.) are expected to get to k1=0.18, which corresponds to 26nm half-pitch with water immersion. Self-aligned spacer/trim (SAS/T) methods (where a deposition step coats a sacrificial spacer pattern with a hard mask, subsequently trimmed, etc.) are projected to approach k1=0.13 (19nm hp), both well below the single-resist k1=0.25 limit. In spite of the evident difficulties-litho CDU specs below 3.5% and overlay at 7% for DEDE but up to 20% for SAS/T, etc.-February’s expert panel predicted that the NAND manufacturers (at least) would do it.
Don Samuels of IBM introduced the litho user’s perspective by countering that DPT was a last resort, being developed in IBM alliances for prototyping, but not necessarily for production. However, the very restricted design rules required for a product to be built using DPT pointed toward improved yield with less exotic techniques. Methods devised for alternating phase shift mask designs were being re-applied.
Robert Bigwood of Intel observed that the DFM strategies that had to be implemented for DPT were not disruptive and need not lead to a great increase in time-to-silicon, especially if tasks were done in parallel. However, the mask data prep volume was going to be larger. Luigi Capodieci of AMD noted that there was a trade-off between process complexity and material sophistication. For example, a practical nonlinear resist or CEL could make the second coat and etch steps of DEDE unnecessary. Even so, materials companies are not actively seeking materials that would facilitate DPT, even simple ones like negative 193nm resist.
Mircea Dusa of ASML pointed out that DPT would be a challenge to the entire production system, not just lithography. In particular, etch bias would be a major CDU contributor and metrology needed to be improved-quickly. He suggested that metrology tools could be used for compensation, not just dispositioning, so that anomalies like a reticle CD fingerprint on one exposure could be compensated in the second using a pre-distorted dose profile, for one example. Dedicated tools might be needed, though, both for exposure and metrology, ending “mix-and-match.”
Dusa also presented a paper from Mireille Maenhoudt of IMEC that sketched numerous double patterning options, from “freezing” the first resist pattern (thereby reducing the number of hard masks needed) to double development, where the highly exposed regions of resist dissolve in a positive-tone developer while unexposed regions are removed in a negative-tone developer, leaving a grating with half the exposed pitch. It remains to be proved that all the CDs can be controlled sufficiently to yield working circuits, but the proof-of-principle experiments have been done, he said.
Speakers from EDA companies Cadence and Mentor Graphics emphasized that DPT litho tools must be embedded in today’s designer flows, without disruption-fabless companies are fabless because they don’t want to know manufacturing details, even crucial ones. Nevertheless, there is a successful example of design interfacing with sophisticated manufacturing models: RET.
Maskmakers and tool vendors seemed remarkably sanguine about DPT, perhaps because of the possibility of increased volume. Takihashi Kamikubo of Nuflare, the dominant manufacturer of e-beam write tools, pointed out that scanner alignment errors dominated mask effects. The low stress mask blanks and charge dissipation layers thought to be needed to meet the demands of double patterning already exist. Bill Broadbent of KLA-Tencor claimed that their 600 series defect detection tools would meet the “basic requirements” of 32nm DPT masks in 2009. However, he did note that the company offers no placement metrology tools, and the 600 would not detect the displacement of an entire region of a plate. Jun Wei Bao of Timbre Technologies suggested that scatterometry-based methods would soon achieve sufficient overlay and CD sensitivity for 32nm DPT.
Han-ku Cho described the present state of the art of DPT achieved by Samsung, which does not expect any other litho solutions to be available by 2009. He pointed out that the scanner stage randomness consumed 60% of the error budget in DEDE, motivating SAS/T techniques, and asked for accelerated development of an image placement metrology tool sufficient to fulfill the DPT registration specs.
Images of hamburgers with one, two, and four patties were served up by DNP Fellow Naoya Hayashi to illustrate the challenges of multiple patterning lithography. Overlay becomes more challenging as the number increases, but DFM restrictions are reduced because more geometries can be separated without conflict when the mask set is larger. Because of manufacturing efficiencies and quality trade-offs, the cost of a DPT mask set would only be 1.7× that of a comparable single mask, not 2×-just as a double hamburger does not cost twice as much as a single patty, he explained.
Franklin Kalk of Toppan Photomasks concluded the usually dour maskmaking symposium with a remarkably optimistic view: It is all do-able! He claimed that the “random” placement errors characteristic of certain e-beam mask writing tools are not random at all, but correctable systematics related to the position of the beam in the physical lens aperture, which is not presently modeled or measured. So while tool development is necessary, it is not impossible to understand and correct the errors with the most impact. In addition, when 32nm logic actually has a minimum pitch of 90nm, Kalk claimed it is possible to meet the 5nm overlay spec by selecting the best masks from current production. Even 1nm CD will be doable if all of the improvements that maskmakers know about-but have found uneconomical to apply-are actually implemented, he predicted. M.D.L.
Electron transport via quantum tunneling in metal insulator diodes
The humble diode is the focal point of what Phiar Corp. hopes will be the beginning of a future that includes nonsemiconductor materials for junction transport via quantum tunneling-and the first credible alternative to semiconductors since the vacuum tube era.
Potential applications of the company’s metal-double-insulator-metal (MIIM) diodes include:
- 60GHz+ wireless communications (addressing antenna-edge frequency conversion);
- Millimeter wave radar;
- Millimeter wave and terahertz imaging and spectroscopy;
- Next-generation flash memory (enabling direct addressing at NAND densities); and
- Chip-to-chip RF communications (reducing copper interconnects).
Motorola Labs has gone on record validating the high-speed performance of MIIMs for future wireless applications, stating in a joint news release that Phiar’s diodes surpass the benchmarks of commercially available diodes for millimeter wave detector applications (Fig. 1). A joint paper presented at the 2007 IEEE RFIC Symposium discussing measurements taken at Motorola support that claim, noted Adam Rentschler, director of business development at Phiar.
 Figure 1. Benchmark tuned detectors. (Source: Phiar) |
MIIM devices are made of amorphous films deposited at temperatures below 300°C. Phiar says it has proven the technology on several substrates-CMOS, post-CMP CMOS, SiO2, quartz, and polymide. RF signal integrity is optimized by locating passives, antennas, and detector diodes on the same substrate.
 Figure 2. a) Physical structure and b) quantum behavior of a MIIM diode. (Source: Phiar) |
Devices built with the MIIM structure, which uses nanoscale stacks of metals and insulators instead of traditional compound semiconductor materials, offer two primary speed advantages over semiconductors, according to Rentschler. “First, traditional semiconductor junction transport is replaced by quantum tunneling, a phenomenon so fast it requires only about one femtosecond,” he told SST. “Second, in metal-insulator devices, bulk electron transport takes place in metals, rather than much lower mobility semiconductor materials” (Fig. 2).
Much of the projected major cost-savings in the MIIMs process flow come from the ability to use existing sputtering equipment as well as eliminating the need for exotic compound semiconductor materials, Rentschler explained. Additionally, because the nominal device linewidths are 300nm, there is no need for cutting-edge lithography. “Currently, we only need four mask layers-that number will probably start to increase a bit when we start building more sophisticated analog ICs, but that number is still small compared to the number of mask layers one would normally find in a typical CMOS process,” he said. The 60GHz diodes developed for Motorola measure roughly 300nm × 300nm, dimensions easily achieved with older manufacturing technology.
The company is careful, though, not to make claims about supplanting Moore’s Law. “Those working at the cutting edge of semiconductor technology continue to do amazing things and keep inventing around seemingly insurmountable challenges,” Rentschler told SST. “But there is now an alternative to incremental performance improvement in semiconductor technology. Metal-insulator electronics is a brand new platform for engineers to utilize, particularly in applications requiring low cost, high performance analog devices.”
RF engineers may become enthusiastic as this technology is deployed. According to the company, its metal-insulator electronics offers the ability to tap not only the 7GHz of unlicensed spec-trum centered around 60GHz, but also the same-sized chunks the FCC has allocated at 120GHz and 244GHz. “The devices stay the same,” said Rentschler, “but the antennas shrink to handle the higher frequencies.” He added that Phiar plans to eventually build chip-to-chip RF interconnects at carrier frequencies of 500GHz or higher.
Another application being explored, according to Rentschler, is flash memory, where “there’s always a need to achieve greater density and greater speeds.” He wouldn’t elaborate on details, citing a confidentiality agreement, but noted that Phiar’s technology enables the fabrication of a very high-current density, very small-switching diode that’s compatible with CMOS and proprietary flash memory technology. D.V.
Intel finds signs of heterogeneous life after silicon
CMOS circuits using silicon channels are hitting the performance wall, and doping with germanium and straining the lattice have already been used to push the limits. Thus, compound semiconductors are again under consideration as building blocks for mainstream ICs-this time integrated on top of 300mm silicon wafers. High-k and metal-gates (HK+MG) have been spun as the biggest change in 40 years, but integrating compound semiconductors with silicon will be a far greater challenge because it will require even more new materials. Now Intel researchers have reported passing a milestone along the road many travel to heterogeneous integration: integrated superior device performance.
Earlier this summer, Intel researchers achieved success at fabricating high-performance devices using both indium antimony (InSb) and indium gallium arsenide (InGaAs) channels, and in each case they perform as well as their counterparts on GaAs wafers. In an internal blog, they showed curves for the performance of both types of devices, with individual transistors both higher performing and consuming less power than equivalently sized silicon devices.
Mike Mayberry, Intel’s director of components research, articulated five general areas of research and development needed to create a competitive commercial heterogeneous semiconductor fab technology:
- Put compound semiconductors on silicon wafers,
- Find different high-k dielectrics for the gates,
- Develop pMOS materials to go with known nMOS,
- Develop enhancement-mode devices instead of depletion-mode, and
- Make them small enough to compete with silicon transistor densities.
The last area is the tricky one. These circuits are conceived of as being possible at or past the 22nm node, so that means the high-yielding dense 32nm and likely 22nm CMOS circuits will already be in production using strained SiGe. Heterogeneous circuits will have to compete with Si/SiGe chips on price, so transistor packing density will be crucial.
By the time InSb and InGaAs can be integrated on silicon wafers, finFETs should also be options along with planar transistor structures. “It is possible that in the timeframe we’re discussing that trigate structures could be a strong candidate, and that builds pressure to find a vertical solution for III-V,” Mayberry told SST in an e-mail exchange. However, he admitted that “we do not as yet have a solution to that problem.”
If finFETs are used, new metal alloys will need to be developed to be able to form minimal-resistance electrical contacts to these new materials. Even if planar structures are used, the contacts will almost certainly be to the channel material instead of silicon to avoid the need for a >5nm transition zone from material to material that would otherwise limit packing density. Due to the need for this transition layer in planar devices with silicon contacts, and the performance advantages to a reduced number of boundary layers, it seems likely that metal contacts will be direct to the new compound semiconductor materials.
Mayberry confirmed only that “we have not decided how to make electrical contact for those future devices.” One thing he knows is that for Intel’s current work, SOI would just get in the way and everything is grown on bulk silicon wafers.
Mayberry’s blog indicates that Intel will show enhancement-mode device results using these materials at IEDM in December. Since these newest devices will be “normally off” they should result in minimal leakage and reduced power-consumption for circuits. We can almost certainly expect unexpected subtle second-order integration challenges with all of these new materials, with the semiconductor industry now moving into “interesting times.” E.K.
Pyxis banks on single-pass manufacturability and yield optimization
Building on its relationships with partners PDF Solutions, Ponte Solutions, and Brion Technologies (recently acquired by ASML), Pyxis Technology has launched its Nexus Solution Suite, having matured the product through implementation on 60 different designs, and working with a number of IC manufacturers including AMD and Chartered Semiconductor Manufacturing.
According to Mitch Heins, VP of marketing, the need for the company’s technology arises not only from the need to start with a “fresh sheet of paper” with respect to the traditional iterative approach to physical design. Pyxis has set out on a design-based DFM approach that implements a single-pass approach that concurrently looks at routability closure, timing closure, manufacturing closure, DFM rules, etc. The resulting layout is thereby optimized for yield.
To illustrate the yield benefits achievable with Pyxis’ NexusRoute software, an IC routing platform architected for designs ≤65nm, Heins provided data on a benchmarking study showing how predicted yield using the company’s auto-router compares with other commercially available routers (see figure). The figure shows results from six different benchmarks, four of which were manufactured at 90nm and two of which were manufactured at 65nm technologies, he explained.
 Design-limited yield improvement (random and systematic yield) potentially improved by >10% in sub-65nm. (Source: Pyxis Technology) |
Each of the benchmarked designs is a production design for which the fab yield is known and simulated using yield analysis tools from its DFM partners, Ponte Solutions and PDF Solutions. The results were correlated to the known fab yields, Heins told SST, and then re-routed with NexusRoute “using identical standard cell and macro placements and timing constraints,” he noted. The Pyxis version of the designs were re-simulated and compared against the original version of the design to generate the results in the figure. In all cases, the Pyxis routed design showed an improvement in the simulated yield ranging from 5.1%-11.1%. -D.V.
Annealing process speeds up self-assembly for sub-30nm features
Researchers at the National Institute of Standards and Technology (NIST) say they’ve come up with a new “cold zone” annealing technique that processes block copolymers and other thin films to align into regular patterns of nanocylinder lines, which when chemically removed offer a pattern template for building advanced microstructures.
Typical oven annealing for block copolymer thin films causes one of the two polymers to segregate into the nanocylinder lines as little as 5nm apart, or with equally regular arrays of nanoscale dots. Traditional oven annealing can’t produce high-enough quality films, and a “hot-zone” anneal-where thin films are slowly moved through a heated region to reach a temperature just beyond the point where the cylinders become disordered-offers a low-defect approach but little orientation control, and the temperature threshold is too high to prevent degradation for some copolymers, NIST explained in a statement.
So, the team developed a “cold zone” annealing system that not only processes the copolymers well below the order-disorder transition temperature, but also “repeatedly produces a highly ordered thin film in a matter of minutes.” Also, tweaking the annealing conditions modifies the cylinder alignment. The orientational correlation lengths measured after approximately 5hrs above the glass-transition temperature were ≈2µm, an order of magnitude greater than that obtained under equivalent static annealing, according to the researchers’ Sept. 12 report in Nano Letters.
Being able to process polymers much more quickly at these transition temperatures “suggests zone annealing [may be] a route toward more robust nanomanufacturing methods based on block copolymer self-assembly,” the NIST researchers wrote. Yields have been shown to be “product quality,” and there are “virtually no limitations on sample dimensions.” The method is being evaluated for fabrication of highly ordered sub-30nm features, although more work is needed to better understand exactly why the cold zone annealing works so much better, and to refine the measurements for evaluating results. J.M.