Improving yield through parametric variability characterization and modeling
11/01/2007
EXECUTIVE OVERVIEW
Random and systematic process variations reduce parametric yields significantly at the leading 65nm and 45nm CMOS process technologies. Parametric yield, distinct from the traditional notion of defect-limited yield, reflects how variations in physical characteristics such as line width, line edge roughness, dielectric thickness, and MOSFET channel dopant density alter electrical characteristics that in turn create device and interconnect performance variations. The resulting circuit timing and power variations degrade yield, yet these variations are stochastic in nature, and not adequately described by purely deterministic physical models that have been the mainstay of physical CAD. Direct measurement of parametric variability across the die as well as across the wafer is needed. A methodology that addresses parametric variability across-die and across-wafer is presented.
The local and long range variations of electrical parameters exhibit systematic as well as purely random components. Quantifying these components, as well as important correlation among electrical parameters, requires a comprehensive set of process characterization data. Semi-empirical models of device and interconnect that are based on a combination of measured statistics and suitable physical models provide an effective approach for circuit variability simulation. In these models however, key electrical parameters must now be considered as correlated, random variables.
Systematic vs. random sources of variability
Sources of variability manifest themselves on characteristic time and/or distance scales. Focusing on spatial variability, long range variations (i.e., those with low spatial frequency) arise due to systematic physical processes that may be described by deterministic physical models. An example is the variation in polysilicon or metal interconnect thickness due to the dependence of chemical-mechanical polishing on feature density within a region tens or hundreds of microns in extent. Short-range variations (those with high spatial frequency components) arise due to both systematic and random processes. Lithographic patterning is a good example of a source of short range systematic variation since optical intensity patterns interact over a scale of a few microns and depend upon photoresist and illumination parameters in a reasonably deterministic way.
 Measured poly line resistance variability in a sub-100nm CMOS process. |
When random processes impact device performance, they degrade the efficacy of deterministic physical models. Returning to the short range patterning example, the final pattern will depend upon the lithography step [1] and the pattern etch step. On the very small distance scale characteristic of the width of the line being formed (say, a 65nm polysilicon gate), local chemical processes create a locally random component of the etch rate that produces a variable physical gate length along the width of the transistor. A physical model of this etch process is prohibitively complex; likely involving an atomic level, probabilistic treatment in order to accurately model not only the resulting mean width, but also the width variation of the gate. A semi-empirical model that combines gate length statistics extracted from measured electrical data with deterministic lithography simulation offers a more practical modeling alternative.
Yield modeling demands accurate statistics, however in many cases, standalone physical models simply do not capture all the relevant physical mechanisms that impact yield. Semi-empirical models that capture direct measurement of process statistics are necessary. To further illustrate the degree of modeling challenge with the above patterning example, the depth of focus, which is directly influenced by the uniformity of the chemical mechanical polish of the underlying film, will influence the width of the gate poly. So, the actual gate length is impacted by long range and short range systematic variations as well as by random etch processes.
An awareness of systematic and random variability is not new, but the need to model it accurately and inject this information into the design flow is. Consequently, the direct measurement of device and interconnect variability, especially in electrical parameters related directly to parametric yield, has become essential in the sub-90nm process technologies.
Measurements complement process/device simulation
The strongest approach for building models for statistical design is to marry powerful automation techniques with a much richer set of process data than what has historically been used. Sophisticated technology CAD (TCAD) tools simulate complex physical processes of individual manufacturing steps (lithography, etch, deposition, ion implantation, etc.), as well as transistor electrical behavior. Such tools model the linkage between process steps and device/interconnect performance, but the core physical models employed often do not comprehend the variety of (and the interactions among) stochastic processes that contribute significantly to parametric yield. An electrical metrology that captures device/interconnect statistics within-die complements the application of deterministic CAD.
Correlation between random variables, for example, can strongly influence the statistical properties of a system. Spatial auto-correlation, defined by the covariance between two different instances of the same random variable at different distances, will alter the statistical behavior of a spatially distributed circuit. Statistical static timing analysis must incorporate models of such phenomena in order to be accurate. Auto-correlation is best modeled with actual measured data due to the complexity of the distributed system and the physical phenomena that impact correlation.
Statistical process characterization and modeling
Variability die-to-die, wafer-to-wafer, and lot-to-lot, has historically been minimized by process engineers in an effort to achieve a robust and stable manufacturing process. Test structures replicated with each die provide statistics for the analysis of very long range (across wafer) systematic effects. For distance scales smaller than the die size, within-die statistical analysis is required to quantify long and short range systematic variability, and random variability. Creating test vehicles to measure statistics across the die has historically posed practical challenges.
Naturally, increasing the number of test structures to improve statistical sampling within-die increases the mask area required. During process development, masks sets dedicated to process characterization provide a large mask area to work with, but the many thousands of different test structures required for device performance, design rule, and reliability optimization fill the mask, leaving little room for replication. In a production process, only the scribe line is available on product masks for characterization purposes, severely limiting the number of test devices available with conventional test structure approaches.
The solution is to create arrays that allow greater packing density of test structures [2]. Active circuitry is used to provide addressing to individual test devices within the array and electrically isolate unselected devices. By effectively sharing the probe pads required for wafer level test, array-based techniques improve overall area density by a factor of ten to more than a hundred. For certain types of characterization, the density improvement can be closer to a factor of a thousand, depending on the features and design of the array.
Test structure arrays enable efficient short and long range variability characterization within-die. The figure shows silicon results of an array-based test of poly line resistance as a function of width for a sub-100nm process. The regular structure facilitates extraction of spatial auto-correlation information from sub-blocks of the array containing identical devices. When systematic variations are suitably extracted from the data, the remaining local random variability supplies information of the distributions of circuit modeling parameters (e.g., threshold voltage). The empirical models of systematic trends supply statistical timing analysis tools with ‘de-rating’ models. Local distribution and correlation models of circuit modeling parameters supply statistical circuit analysis engines using Monte Carlo (or other) sampling techniques.
A challenge faced by array-based statistical process characterization involves the time required to test. Conventional wafer-level parametric test methods and hardware are being improved to increase the throughput of required analog variability tests. This is especially true of production wafer applications of scribeline arrays. Massively parallel parametric testers are beginning to appear to address this throughput issue.
Conclusion
The time and expense required to run wafers and test them will always ensure that physical simulation plays a role in creating advanced models for circuit simulation. Characterization of parametric variability is nonetheless viable using array-based approaches that ride on process development test masks, multi-project wafers, or in the scribeline during volume production. When coupled with new test time reduction methods, high density test vehicles become practical sources of real statistical information that will drive statistical design and improve parametric yield.
References
- Orshansky, et al., “Characterization of Spatial Intrafield Gate CD Variability, Its Impact on Circuit Performance, and Spatial Mask-Level Correction,” IEEE Trans. on Semiconductor Devices, Vol. 17, No. 1, pp. 2-11, February 2004.
- K. Doong, et al., “Field-Configurable Test Structure Array (FC-TSA): Enabling Design for Monitor, Model, and Manufacturability,” Proc. of the International Conference on Microelectronic Test Structures, IEEE March 2006.
Jim Bordelon received his BS degree in electrical engineering from The Georgia Institute of Technology, and his MS in electrical engineering and his PhD from the U. of Texas at Austin. He is president and CTO at Stratosphere Solutions Inc.
Prashant Maniar received his BE in electronics engineering from U. of Mumbai, his ME in electrical engineering from the U. of South Carolina, and his MBA from Santa Clara U. He is chief strategy officer of Stratosphere Solutions Inc., 155-A Moffett Park Drive, Suite 220, Sunnyvale, CA 94089 United States; ph 408/215-0074, ext. 9651; e-mail [email protected].