Photomasks: Is nucleoepitaxy in the future?
11/01/2007
The semiconductor industry’s growth over the past 50 years has been fueled in part by a host of lithography innovations. The key innovations related directly to the photomask include the reduction stepper, the pellicle, the electron beam mask writer, mask inspection and repair, and resolution enhancement techniques (RETs). Each of these addressed a technical challenge and ultimately lowered manufacturing cost.
Reduction stepper. With 1× lithography, the photomask was an exact replica of the entire wafer-level die array to be imaged. Photomasks were produced by a tedious process in which a photorepeater imaged the die array onto the mask from a master image on a reticle (a mask containing an image of a single die). The GCA DSW4800 reduction stepper moved the photorepeating process to the wafer and eliminated the slow and costly reticle-to-mask process step.
Pellicle. The reduction stepper introduced a defect challenge. Because the stepper prints the image that has been etched on the photomask multiple times onto the wafer, mask defects are replicated multiple times. The photomask must be produced with zero printable defects and must be maintained defect-free to prevent wafer defects. Before the pellicle was invented in 1978, masks had to be cleaned frequently, an expensive process. The pellicle captures particles on a film several millimeters above the mask’s image surface, ensuring the particles are out of focus and do not affect image intensity. The pellicle prevents defects and reduces mask-cleaning frequency, thereby increasing productivity and reducing manufacturing cost.
Electron beam mask writer. As feature densities grew in the 1970s, existing mechanical optical pattern generators were unable to provide the desired combination of resolution and throughput. The EBES electron beam mask writer (developed at AT&T Bell Laboratories in the mid-1970s) and its successors enabled precision photomask manufacturing for 25 years. That technology has continued to evolve in the early 21st century with the introduction of variable-shape electron beam systems. Today’s tools write OPC-laden 65nm masks on 1nm address grids with sub-10nm placement accuracy in ~10hrs.
Mask inspection and repair. Mask defects can be a function of time. A photoresist layer may reside on a mask blank for days or weeks (including 10 hours in the mask writer), vs. minutes on a wafer. Keeping a mask perfectly clean for such a long time is challenging. Automated inspection and repair allow the mask manufacturer to verify the pattern integrity and find and repair defects, reducing scrap costs.
RETs (OAI, OPC, and PSMs). RETs represent complexity to the mask manufacturer and the wafer lithographer, but they provide savings in the overall semiconductor manufacturing process because they allow low k1 and, when combined with high numerical aperture (NA), the printing of deep-subwavelength features.
Over the next 10 years, lithography and photomasks will change rapidly, in the following order:
193nm immersion lithography (193i). Water-immersion ArF scanners with NA - 1.35 will enter production, enabling 45nm half-pitch printing. New mask absorber stacks are being developed to suit the high NAs that immersion lithography offers.
Double patterning technology (DPT). To meet the needs of 32nm half-pitch (and potentially 22nm), double patterning will enter production to augment 193i, most likely for flash memory manufacturing first. Pattern splitting and mask manufacturing toolkit accuracy (especially for overlay) are active development areas.
EUV. EUV is expected to be ready for production for 22nm half-pitch technology. DRAM manufacturers may struggle to make DPT work adequately until EUV is production-ready. Critical EUV challenges are source power and the mask manufacturing infrastructure. It is likely that EUV will require RETs when it enters mass manufacturing, which will add another layer of complexity to full implementation of this technology.
In 1957, flying cars and commercial supersonic flight were popular predictions for the dawn of the 21st century. Yet even without delivering those innovations (the Concorde as a mode of transport was not a commercial success, and flying cars are still experimental), the auto and aviation industries have provided tremendous improvements in safety, efficiency, and comfort at affordable cost.
By 2057, the term integrated circuit may still be used, but it will probably not refer to semiconductor electronics as we know them. Size scaling will be an outmoded term, but cost will still be a primary focus, and core deliverables will be functionality, power efficiency, and perhaps “intelligence” (especially if quantum computing techniques bear fruit). Leading-edge lithography will have transitioned to a bottom-up technology based on self-assembly and nanochemistry (or maybe nanobiology). Extrapolating and remapping today’s ITRS, 2057’s integrated circuits should possess about 1 million times the functionality of today’s 65nm chips, consume a few watts of power, and cost about a buck in today’s currency. Can you say nucleoepitaxy?
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Franklin Kalk is CTO at Toppan Photomasks Inc. Contact him at e-mail [email protected].