Interconnect: Future nodes look beyond copper
10/01/2007
EXECUTIVE OVERVIEW
Although copper interconnects have become essential to the continuation of Moore’s Law, they too have limits. Scattering effects lead to exponential increases in resistance as linewidth falls. Design optimizations and enhanced barrier layers can help minimize these effects. Still, 22nm generation devices may force process engineers to consider such radical new interconnect schemes as carbon nanotubes.
One important side effect of Moore’s Law is that technical questions in the semiconductor industry are never definitively settled. Materials and processes that are a perfect fit for current manufacturing may be inadequate in a few years. Ideas that are impossibly complex or expensive now may be essential in the future.
The interconnect process offers one of the most dramatic examples of this evolution. Not so long ago, copper was reviled as poison for transistors. CMP was nothing but a way to erase weeks of hard work. Now, copper is well-established. CMP is a powerful addition to the circuit builder’s toolbox. Even so, the limitations of copper interconnects are becoming clear. In a few more years, manufacturers will need to enhance or even replace the material.
The problem stems from the industry’s steady reduction in feature sizes. Behavior in narrow lines can be substantially different from the bulk properties of the material. For example, models based on bulk properties treat resistivity (ρ) as a constant. Reducing the cross section of bulk wires increases the resistance (R) according to R = (l*ρ)/A, where l = wire length and A = cross-sectional area. As linewidths drop below 100nm, however, scattering at interfaces and grain boundaries becomes more important than bulk behavior. As Gerald Lopez and coworkers at Georgia Institute of Technology showed at this year’s IEEE Interconnect Technology Conference, ρ increases exponentially in this regime [1]. Any reduction in the copper cross-section thus has a double impact, increasing both bulk resistance and the resistivity multiplier. Researchers at STMicroelectronics believe that line resistance at the 32nm node is likely to double relative to the 45nm node [2].
The situation becomes even more difficult in real circuits, with their inevitable dimensional variability. The Lopez group modeled effective resistivity for linewidths below 100nm, considering both size effects and the impact of line edge roughness (LER) (Fig. 1). As LER increases, size effects become more dramatic. Unfortunately, LER depends on the exposure system and resist characteristics. For a given lithography process, LER is a constant, independent of feature size. At linewidths below 22nm, even moderate amounts of LER can be a substantial fraction of the nominal width. Still further resistivity variation comes from CMP, where dishing can be as much as 10% of the total line height.
Finally, Kitada and coworkers at Fujitsu attributed additional variability to feature-dependent copper growth behavior. They found that the copper grain size is smaller in shallower trenches, probably due to the lack of grain growth. Although the Fujitsu group found that RC variability is small at the 45nm node, by the 32nm node it will have doubled [3]. In their model, grain size reduction due to line height accounts for about one-quarter of the total size effect.
Designing for low resistance
The impact of process variation, and of interconnect characteristics in general, depends on the circuit design. According to M. Aimadeddine and coworkers at STMicroelectronics, resistance is more important for long lines, while capacitance has a greater impact on the performance of shorter lines [4]. (A future article will look at advanced interconnect dielectric issues.) Moreover, Lopez found that the average wire length in multicore architectures is shorter: each core has a fixed number of transistors, and therefore a fixed wire length. Single core architectures increase the number of transistors, and therefore the wire length, with each generation. By 2020, multicore systems will reduce average wire length by as much as 62% relative to single core devices. Shorter wires give lower total resistance, mitigating the impact of size effects and interconnect process variations.
At the process level, manufacturers can reduce the impact of variability by increasing the nominal copper cross section. Though resistance remains cross section-dependent, larger wires are less susceptible to the double impact of size effects. Other circuit constraints make it impractical to simply increase the wire size. Instead, manufacturers would like to use thinner barrier layers, allowing more copper to fit within a given lithographic feature.
Thinning down the barrier
Reducing barrier thickness is not so easy, however. The barrier serves two critical functions: preventing copper diffusion into the dielectric, and ensuring strong adhesion of the copper layer. As current density increases, manufacturers are counting on barrier adhesion to improve electromigration resistance. In aluminum, electromigration is a bulk phenomenon, while in copper migration occurs primarily at interfaces and grain boundaries. Adhesion between the copper and its barrier layer provides one of the only available counterforces to oppose electromigration.
To prevent diffusion, the barrier must be thick enough, and conformal enough, to coat the underlying surface completely, with no holes, even as the more porous dielectrics expected at the 32nm node make surface coating more difficult. To encourage adhesion, the material must form a strong interfacial bond with copper. Yet a thick interface layer adds resistance, while miscibility of copper with the barrier can degrade the barrier’s effectiveness as well. Current designs depend on PVD deposition of TaN barrier and copper seed layers. At smaller feature sizes, though, accumulation at the tops of features can shrink or completely pinch off the trench opening, leading to voids and poor quality copper fill. Though ALD TaN layers are less vulnerable to pinch-off and can be thinner than conformal PVD layers, ALD TaN does not adhere well to copper and would require an additional adhesion layer. Ruthenium is one of the most commonly investigated “glue” layers.
M. Abe and coworkers at NEC Corp. observed that highly oriented PVD ruthenium can support direct plating of copper without the need for a preliminary seed layer. Oriented Ru helps control the crystal texture of electroplated copper, improving the grain boundary structure of the resulting film. Ru has lower resistance than Ta, while offering improved copper adhesion. Using ruthenium may also reduce interface scattering and related size effects: Ru-clad lines had 12.4% less residual resistivity than TaN-clad lines. The residual resistivity, measured at 20 K (-253°C), is what remains after eliminating thermal vibrations and is a measure of interface scattering effects. The superior properties of the Ru/Cu interface may be in part because the two lattices are nearly the same size, with only a 6% lattice mismatch, one-quarter of that between copper and tantalum [5].
Unfortunately, although Ru is an excellent adhesion layer, it is not a particularly good diffusion barrier. The most likely structure is therefore a TaN/Ru bilayer, with direct plating of the copper metal. Compared to current barrier structures, this bilayer offers both lower thickness and lower barrier resistance.
Researchers are considering a variety of other “glue” layers as well. In work by Y. Ohoka and coworkers at Sony, replacing the copper seed layer with a copper-silver alloy improved adhesion while increasing resistance by only 1%. Structures with a Cu-Ag seed layer had a 3× larger time-to-failure than standard Cu seed layers. However, the same group achieved even more promising results with a Cu-Mn alloy seed layer. When deposited onto the SiOC dielectric, Ohoka said, this alloy forms a MnOx barrier layer. The oxide offers a 10× improvement in time-to-failure, while reducing resistance of the structure by 15% [6].
Barrier thickness and resistance are especially troublesome for vias, where the need to surround the copper on all sides substantially reduces the available metal volume. Though only silver offers lower bulk resistivity than copper, a thick plug of, say, rhodium, can give lower net resistance than a narrow copper plug combined with the necessary barrier layers. Many integration schemes currently use CVD tungsten vias. This approach is probably not viable for the long term, as CVD deposition of tungsten into very small features leads to voids. Instead, I. Shao and coworkers at IBM found that electroplating of rhodium onto a ruthenium seed layer delivered fill quality comparable to that achieved with copper. The resulting plugs had lower resistance than either tungsten or the copper plus barrier combination, but higher than the rhodium bulk value. Further process optimization may offer even more improvement [7].
Integration of rhodium into a manufacturable process is likely to be extremely problematic, however, because it is a hard, stable, noble metal. Though these characteristics improve mechanical stability and corrosion resistance, they also make CMP-based damascene integration very difficult.
Thinner barrier layers can increase the copper volume in a given line, but the underlying problem of size effects remains. Ever-shrinking feature sizes will eventually drive resistance to unacceptable levels. Anticipating that day, researchers are beginning to consider radical new approaches to interconnect structures. Probably the most important of these is the proposed use of carbon nanotubes, at first in vias and eventually in trenches.
Nanointerconnects look beyond copper
Nanotubes consist of networks of carbon atoms, spiralling around an open core (Fig. 2). They can function as waveguides for current, giving very low resistance and relative immunity to electromigration. Nanotubes come in both semiconducting and metallic varieties. Differentiating between the two is a major obstacle to manufacture of nanotube-based transistors. In interconnects, however, the current simply finds and follows the lowest resistance path.
In the lab, nanotubes can grow when a metallic catalyst is exposed to a carbon-bearing gas at high temperatures. For example, Z. Liu and coworkers at Rensselaer Polytechnic Institute used xylene as the carbon source, with iron from ferrocene as the catalyst. They achieved selective deposition by using an Au/Ti layer to mask portions of the SiO2 substrate. As yet there have been no attempts to integrate this procedure with a full CMOS process flow [8].
Since nanotubes are smaller than most circuit features, a trench or via is likely to contain a bundle of nanotubes. The density of the bundle determines the resistivity of the wire. Though the density of as-deposited nanotubes is limited to about 10 tubes/µm2 by the need to get carbon to the growth interface, the RPI group found that an array of nanotubes immersed in IPA pulled itself together by capillary action. They achieved bundles with about 58 tubes/µm2, a substantial improvement but still far less than the theoretical maximum 1270 tubes/µm2.
Hoyeol Cho and other researchers at Stanford U. modeled interconnect architectures based on copper wire, carbon nanotubes, and optical fiber. For copper and nanotubes, performance decreases as the length of the wire increases, with long lines needing repeaters to achieve adequate signal strength. For optical interconnects, in contrast, the performance and process costs are incurred primarily at the ends, with the conversion from electronic to optical signals and back. The transmission itself is effectively lossless over IC distances. As a result, Cho said, optical interconnects are the best choice for global interconnects. However, they are impractical for local interconnects. Here, nanotubes offer a clear advantage over copper [9].
 Figure 2. Several kinds of carbon nanotubes. (Image by Michael Ströck. Released under the Gnu Free Documentation License and used courtesy of Wikipedia.) |
Yet nanotubes also pose enormous integration challenges, likely requiring a complete redesign of the interconnect scheme. For example, Cho noted that electromigration limits the maximum current density for copper interconnects, thereby restricting the aspect ratio for copper features to about 1.5. Nanotubes do not face this limit, and so the optimal nanotube-based interconnect structure is probably substantially different from the copper-based equivalent.
What about capacitance?
Meanwhile, as noted at the beginning of this article, the problem of interconnect capacitance remains. For shorter wires, capacitance has a larger impact on performance than resistance. Reducing the effective dielectric constant can allow designers to achieve the same performance while reducing the demands placed on the metal lines.
The history of improvements in interconnect dielectrics is not particularly encouraging, however. When low-k dielectrics first appeared on industry roadmaps, forecasters anticipated the dielectric constant would be below 2.0 by now. That didn’t happen: the 65nm node features dielectric constants around 2.5.
While the need for improved dielectric materials has become urgent, serious obstacles to the integration of porous dielectrics remain. These materials are prone to damage during processing and vulnerable to absorption of water and other contaminants. Until new integration schemes actually reach production, interconnect designers have little choice but to push against the limits of copper wiring, stubborn though those limits may be.
References
- Gerald Lopez, et al., “The Impact of Size Effects and Copper Interconnect Process Variations on the Maximum Critical Path Delay of Single and Multi-core Microprocessors,” IEEE Interconnect Tech. Conf. (IITC) 2007, pp. 40-42.
- V. Arnal, et al., “Materials and Processes for High Signal Propagation Performance and Reliable 32nm Node BEOL,” IITC 2007, pp. 1-3.
- H. Kitada, et al., “The Influence of The Size Effect of Copper Interconnects on RC Delay Variability Beyond 45nm Technology,” IITC 2007, pp. 10-12.
- M. Aimadeddine, et al., “Robust Integration of an ULK SiOCH Dielectric (k = 2.3) for High -performance 32nm Node BEOL,” IITC 2007, pp. 175-177.
- M. Abe, et al., “Highly-oriented PVD Ruthenium Liner for Low-resistance Direct-plated Cu Interconnects,” IITC 2007, pp. 4-6.
- Y. Ohoka, et al., “Integration of High Performance and Low Cost Cu/Ultra Low-k SiOC (k = 2.0) Interconnects with Self-formed Barrier Technology for 32nm Node and Beyond,” IITC 2007, pp. 67-69.
- I. Shao, et al., “An Alternative Low Resistance Mol Technology with Electroplated Rhodium as Contact Plugs for 32nm CMOS and Beyond,” IITC 2007, pp. 102-104.
- 8. Z. Liu, et al., “Densification of Carbon Nanotube Bundles for Interconnect Application,” IITC 2007, pp. 201-203.
- Hoyeol Cho, et al., “The Delay, Energy, and Bandwidth Comparisons between Copper, Carbon Nanotube, and Optical Interconnects for Local and Global Wiring Application,” IITC 2007, pp. 135-137.
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Katherine Derbyshire is a contributing editor at Solid State Technology. She received her engineering degrees from the Massachusetts Institute of Technology and the U. of California, Santa Barbara. She is the founder of consulting firm Thin Film Manufacturing, PO Box 82441, Kenmore, WA 98028 United States; e-mail [email protected], http://www.thinfilmmfg.com.