Technology news
10/01/2007
Spike RTA+ms annealing may delay need for metal gates
Results shared at the recent West Coast Junction Technology Group meeting indicated a spike rapid thermal anneal followed by a millisecond laser anneal improves polysilicon gate depletion to the extent that it opens up the possibility of being able to delay the introduction of complex metal gates until the 32nm node for most applications.
Applied Materials’ Susan Felch reported results of experiments done in conjunction with NXP Semiconductors, IMEC, and Matsushita Electric Industrial Co. After first performing RTA, the researchers used a medium-power laser (temperature 1200°C) to perform millisecond annealing. Using this process flow, Felch reported a reduction of 1.4Å in the polysilicon gate depletion (Tinv) for pMOS transistors, while the Tinv reduction for nMOS transistors was 1.5Å (Fig. 1).
 Figure 1. Polysilicon gate depletion improvement (Tinv) with laser anneal after spike anneal. (Source: Applied Materials) |
“When using a metal gate, the object is to reduce the poly depletion thickness down to 0 [i.e., reduce the Tinv thickness to just the thickness of the dielectric itself],” said Felch. “So reducing the thickness of the overall capacitor by 1.4Å is a big step moving in that direction…this should help to delay the introduction of metal gates.”
Another notable finding by this group was that a medium-power laser anneal gave much better overall results for nMOS and PMOS devices than using a high-power laser anneal (1300°C). For nMOS devices, there was an 8% improvement in device characteristics using a medium-power laser vs. only a ~4% improvement using a high-power laser (Fig. 2). For pMOS, there was a 2% improvement using a medium-power laser but no improvement using a high-power laser. By investigating a thermo-mechanical stress model of the gate dielectric interface (SiON) during laser anneal, the researchers attributed the difference in results obtained between medium- and high-powered lasers to induced interface traps that break bonds at the interface of the dielectric. These induced traps, the result of stresses arising because of the difference in thermal expansion coefficients between the polysilicon and the silicon, generate fixed charges in the dielectric (SiON).
Event co-chair John Borland, founder/president of J.O.B. Technologies (and SST editorial advisory board member), told SST that other groups have not seen a degradation in gate oxide or other performance deterioration when using spike RTA first followed by millisecond annealing-in fact, there have been mixed results depending on the group and applications. For example, he cited research at AMD/Dresden in which there was no gate oxide degradation when spike anneal was performed first, followed by millisecond annealing for 65nm volume production. Mattson Technology has also reported that flash lamp anneal (FLA) first followed by spike anneal results in deeper junctions than when spike anneal is done first, followed by FLA. -D.V.
Bosch: Deep etch tools on target for 100µm/min throughput in 2-3 years
Deep etching equipment is about to make a big jump in throughput, according to Franz Laermer, corporate sector research and advanced engineering at Robert Bosch GmbH, and inventor of the widely used Bosch process for deep reactive ion etching (DRIE). Faster volume production will not only bring down the costs of MEMS devices to expand their use in consumer applications and wafer-level packaging, but also make production of 3D interconnect with through-silicon vias (TSV) practical, he told SST partner Nikkei Microdevices.
Laermer reported that recent improvements to the basic Bosch process significantly increase its throughput, and major tool suppliers now developing it further are on track to have 100µm/min etching tools on the market within two to three years.
The relatively slow speed of etching out deep features remains a bottleneck for cost-effective high-volume production. Typical DRIE tools may get throughput of 10-25µm/min, depending on the exposed area, which is sufficient for automotive devices, but still limiting for applications such as consumer sensors and semiconductors. Many producers are expecting deep etch of only 50µm/min by 2010, but now both consumer MEMS makers and chipmakers are demanding higher throughput. 3D interconnect processes are especially limited, often able to etch TSVs at the impractical rate of only a few wafers/hr. With the IC etch market potentially far larger than the MEMS market, tool suppliers are putting resources into developing higher throughput tools.
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The key is increasing the energy input without increasing the disturbances in the plasma that result in uneven etching, and minimizing the passivation time between etch cycles. The Bosch process etches down vertically by alternating etching and passivation, bombarding the silicon with high energy plasma to carve out a hole, then coat it with a layer of Teflon-like polymer film to protect the sidewalls from further erosion before the next round of etching. Researchers have increased the voltage feed to 5kW, but introduced the high-frequency voltage to both ends of the coil that induces the plasma instead of just one, to produce a more symmetrical plasma. An added delay line shifts the phase of one end by 180°, so each end cancels out the uneven flow patterns generated by the other. This simple approach limits the usual capacitive coupling, taming the electrical fields in the plasma that produce displacement currents and uneven plasma density, which result in uneven etching. A magnetic field added within the chamber further aligns the plasma shower so it hits the wafer vertically, for more uniform etching at high power.
 Figure 2. Spike anneal + LA enables drive current and short channel effect (SCE) improvements. (Source: Applied Materials) |
The process uses the usual SF6 etchant and C4F8 passivation gases, but delivers them at 10Pa high pressure so they hit the wafer at higher speed, 1000cm3/min at atmospheric pressure. The passivation phase is cut to 100-200ms for 1-2 sec of etching, using a pump that emits etchant gas by default, with a valve that switches over for quick bursts of passivation gas as needed. -P.D.
Ion sources get a new lease on life with in situ chemical cleaning
Buildup of chemical residues inside an ion implanter limits the tool’s overall utilization efficiency. James Dunn, Atmel Corp.’s equipment engineering section manager, described for SST the results of the company’s evaluation of a new in situ chemical cleaning technology from ATMI that reduces such deposits and achieves greater predictability for source change-outs.
Deposit build-up is one cause of ion beam instability, which in turn adversely affects process integrity. Two major problems arise from ion beam instability. One problem is momentary drop-out in the beam current on the wafer being processed because of high-voltage arcing, which leads to undesired species being implanted into the process wafer for a certain period of time, according to Dunn. Such high-voltage glitches result in the nonuniformity of implants and particle contamination. Another kind of beam instability causes drifting of the beam current, which leads to dose errors. These process integrity problems lead to unpredictable change-out of the ion source.
 Effect of in situ cleaning on ion source life. (Source: Atmel Corp.) |
While source lifetimes vary according to implanter type (i.e., medium-current vs. high-current) as well as application, according to Dunn, a typical medium current implanter application at Atmel might see a variation in source life between 200-500 hrs, when the actual filament life should be 500 hrs.
During Atmel’s evaluation of ATMI’s AutoClean process-an in situ process that introduces a cleaning agent at regular intervals into the ion implanter-Dunn told SST that 100% of the sources subjected to the purge process have gone to the end of filament life (500 hrs), and even higher in some cases (see figure). During the evaluation, process qualifications and particle checks were done, and the results indicated no harm was done to the wafers using the new cleaning technology.
According to Dunn, the fab’s population of medium current implanters has averaged 292 hours of source life, which translates to 27 source changes per tool per year. The two sources running AutoClean have averaged double that lifetime (588 hrs) with the third source still running stable with 501.28 hrs, he said, and the company expects its annual source changes to drop to 13-14 per tool per year, “thereby reducing our costs for cleaning and consumable parts by 50%.” Dunn noted that the source changes average 5hrs to complete, involving the actual source change and also tool re-qualification, so fewer source changes with the new tools “translates to 65 hrs of additional production time per tool per year, and a reduction of one-half the process qualifications, which frees up additional processing and metrology equipment in the fab.”
An additional benefit of using the new technology cited by ATMI is the ability to do species rotation, for example, being able to run a phosphorus process immediately after a boron process or vice versa. Having the ability to be flexible is becoming more important as fabs need to have shorter reaction times to respond to customer demand. -D.V.
Optical deep trench inspection keeps DRAMs out of the red
Manufacturing of deep trenches poses great challenges, especially the etching of deep, high-aspect ratio (>20:1) bottle-shaped cavities into the silicon substrate. In particular, the sidewalls of high-aspect ratio trenches may collapse during the isotropic wet etch step, so a fast and non-destructive technique is needed to inspect for such damage. Vistec Semiconductor Systems GmbH, Weilburg, Germany, has worked with Qimonda in Dresden to develop a new in-line optical inspection technique for deep-trench DRAM structures.
 Vistec LDS3300 full wafer image of 90nm node DRAM cells with merged trenches reflecting red light. (Source: Vistec Semiconductor Systems GmbH) |
Typical trench metrology methods including scatterometry, wafer mass measurement, model-based IR spectroscopy, and atomic force microscopy are all limited in wafer throughput. By using an automated macro defect inspection system (Vistec’s LDS3300) with special illumination and optimized analysis software, the visualization and detection of merged trenches in high-volume trench-DRAM production became possible. The tool scans full 300mm wafers at speeds of up to 130 wafers/hour, fast enough that 100% inspection can be used for excursion monitoring.
The tool uses very strong broadband strobe lights, which are synchronized to the x/y-stage and with that to the wafer. The angle of incidence of the strobe lights is optimized so that correctly formed trenches reflect almost nothing, while merged trenches reflect red light (see figure, p. 24). Special analysis software translates the strength of the reflected signal into pseudo color data. With that, the setup of a threshold for automatic detection of merged trench problems is possible.
The results are claimed to be highly repeatable and reliable, providing substantial data for process control and optimization while lowering overall costs. Qimonda in Dresden says that it has helped speed up both learning cycles in development as well as production ramps, and response time to excursions was shortened. Vistec is selling the system worldwide. -E.K.
Lam, Novellus both strip wafer edges
Silicon wafer edges induce inherent non-uniformities in processing, and also seem to be the main source of defects for immersion lithography. Cleaning/stripping the wafer edge (or “bevel”) is thus essential for production yield. Advanced fabs today typically specify a 2mm edge exclusion for wafers, and Novellus Systems Inc. and Lam Research Corp. have responded with new hardware to dry strip edges.
Novellus’ downstream dry edge strip. Depth-of-focus along with etch-rate selectivity challenges have led to the need for hard masks in advanced IC lithography. An amorphous carbon PECVD thin film that is “ashable” may be formed using a wide variety of hydrocarbon precursors, though deposition parameters must be properly controlled to ensure the final film structure is composed of sp2 carbon bonds for transparency and film stability. “We’re getting 20:1 selectivity, and extinction coefficient value at 633nm of 0.11,” claimed Julian Hsieh, senior director of product management for Novellus’ dielectrics business group.
To eliminate any edge particles that could kill dice, the company’s Vector Express PECVD tool now provides a new dry edge-bead removal (EBR) capability into the outgoing loadlock. Using an off-the-shelf downstream plasma generator to crack O2 into mono-atomic oxygen (Fig. 1), amorphous carbon (red in the figure) is stripped off the wafer edge while the top surface is masked by center shield hardware.
Field-retrofittable to the Vector platform, the EBR has additional potential applications. Since mono-atomic oxygen is extremely reactive, it may be able to clean other PECVD films off of the edge/bevel of wafers. “If you have this capability, you may be able to use it to solve other problems,” admitted Hsieh.
 Figure 2. Schematic cross-section of a wafer edge being stripped by the plasma ring in a new chamber available on Lam’s 2300 platform. (Source: Lam Research Corp.) |
Lam’s plasma ring edge strip. Meanwhile, Lam now sells a plasma edge clean module that can be part of a cluster on the company’s 2300 hardware platform. A capacitively coupled plasma is shielded from the wafer topside by a shield precision engineered to float fractions of a millimeter above the wafer surface (a gap too small to be seen in Fig. 2). No electrostatic chuck is used to minimize cost.
Yield improvements of 1%-4% are possible using rigorous dry edge strip, according to Rick Gottscho, group VP and GM of Lam’s etch business, adding that a 3-4 chamber cluster of these edge strippers may see production. Lam claims to be engaged with 18 of the top 25 capital spenders. “Most of our customers today are in evaluation phases, looking at the yield benefits, and the applications first to use it, but the pull is very strong,” said Gottscho. He said that chamber throughputs are close to what you’d expect from a stripper dealing with low-k etch processes.
Both Novellus and Lam have released useful tools for high-volume production, and both use a hardware shield to protect wafer top-sides while stripping films from edges. However, they are inherently different in the plasma hardware. Novellus’ remote generator design is safe and simple and fits into a load-lock without taking up chamber space. Lam’s capacitively coupled plasma ring provides an additional degree of processing freedom with ion bombardment, but requires the space of a process chamber to do so. -E.K.