SiP and SoC will remain co-existing system solutions
10/01/2007
EXECUTIVE OVERVIEW
System-in-package (SiP) and system-on-chip (SoC) approaches provide different advantages for different end-market applications. SiPs allow for relatively easy hetero-integration of analog and RF functionalities with digital CMOS, with possible cost and performance benefits. However, proper system partitioning at the design stage is key to obtaining the maximum value from a SiP. SoCs provide the lowest manufacturing cost, but design costs are often higher and time-to-market is generally slower. Depending on the anticipated unit volumes and target ASPs for the required system, either approach may be desirable.
If you can implement it in CMOS, design it fast enough to meet your time-to-market deadline and sell it in high volume, then a SoC will nearly always be the cheapest and smallest solution. Driven by the International Technology Roadmap for Semiconductors (ITRS), the semiconductor industry has made Moore’s Law a self-fulfilling prophecy, maintaining CMOS as the densest and cheapest semiconductor process in which to implement silicon transistors.
Produced in 90nm CMOS, for example, AMD’s Athlon 64 X2 microprocessor packs around 230 million transistors onto approximately 200mm2 of silicon. In terms of cost, 90nm CMOS SoCs, such as NXP’s latest baseband processors for mobile phones, implement advanced multimedia capabilities for just a few dollars.
But are these highly integrated CMOS SoCs really system solutions? A SoC that integrates a RF transceiver, for example, is still likely to need external components such as an antenna switch and filter that will need to be designed and assembled onto a PCB. Even purely digital systems frequently need external components such as decoupling capacitors, frequency reference crystals, timing capacitors, and electrostatic discharge protection networks. An increasing number of companies in the fast-moving consumer electronics area generate their market value at brand level rather than at electronic design level, so the ideal goal is true plug-and-play components supported by reference designs that can be copied. However, that is not always what a SoC solution provides.
Providing companies with the extra level of integration required to approach a total-system solution is where SiP technologies have found favor. In practice, these SiP solutions go by many different names depending on the method of integration employed. Multichip module (MCM), multichip package (MCP), package-on-package (PoP), and stacked dice are all examples of SiPs. What differentiates them from SoCs is that they all integrate more than one die into the package.
Technology partitioning
How the system is divided up between multiple dice depends on the technology partitioning. The decision is influenced by a number of different factors such as cost, performance, size, reliability, and design effort. As a result of these different factors, even though a system can be implemented in a single CMOS process technology, it may not necessarily be ideal to do so.
Consider, for example, a system containing a CPU, several hardware acceleration units, and a significant amount of DRAM. Although the DRAM could be implemented in a baseline CMOS process, the additional mask steps required to implement it efficiently in terms of chip area may result in a significant increase in chip cost. Large memories are normally fabricated using optimized process technologies, which are significantly less expensive than those used to fabricate the rest of the system.
A two-die solution in which a CPU/hardware-accelerator chip and DRAM chip are assembled into the same package using a stacked-die (Fig. 1) or PoP approach may then become an attractive alternative. It is typically with this type of technology partitioning, where both dice could theoretically be implemented in a CMOS process, that today’s SiP versus SoC debate has arisen. As CMOS process technologies have acquired RF capabilities, the debate has broadened to include the options for silicon solutions in mobile telecommunications.
 Figure 1. A typical stacked die package-on-package (PoP) combines memory and logic chips into a SiP. |
In truth, however, SiP and SoC are not competing approaches. Modern integration technologies already extend a long way beyond the CMOS processes that have delivered a continuation of Moore’s Law for the last 40 years. New silicon-based technologies for low-cost passive component integration and the silicon integration of advanced RF components such as micro-electromechanical systems (MEMS) devices and bulk acoustic wave (BAW) filters mean that far more functionality can be drawn inside a SiP package than can be integrated on conventional CMOS chips. These new technologies do not replace the CMOS dice; they add to them, such that the latest SiPs typically comprise SoCs (‘More Moore’) plus additional functionality (‘More than Moore’). However, customers are normally only prepared to pay for the cost of the extra level of integration provided by a SiP when it offers real added value.
 Figure 2. The twin-eye laser sensor from Philips integrates optical lenses into the same package with a control ASIC chip. |
SiPs are also beginning to progress beyond the realms of pure electronic systems, for example, through the integration of optoelectronic devices and optical systems into the package. Figure 2 shows the twin-eye optical PC laser mouse sensor from Philips Laser Sensors, which integrates lenses for its two optical lasers directly into the package. This SiP also contains a dedicated application-specific integrated circuit (ASIC) that performs all the necessary digital and analog signal processing for mouse displacement calculation, laser power saving, and eye-safety management functions.
System-level know-how is key
If technology partitioning lies at the heart of all SiPs, then the key to producing high-performance cost-effective SiPs is getting this technology partitioning right. Doing so requires a thorough understanding of the application at the system architecture level, so that the consequences of shifting specific functionality from one technology implementation to another can be explored. This is where semiconductor manufacturers that have a broad range of process technologies in-house have a distinct advantage, because they can design the individual components of the SiP specifically to fit the chosen architecture.
Module makers who have to source components from different manufacturers inevitably loose some control over the design of those components, making it significantly more difficult to achieve optimal system partitioning. In addition, SiP technology is moving rapidly towards wafer-scale manufacturing and chip-scale packaging, putting both silicon fabrication and SiP assembly squarely in the realm of semiconductor companies.
Whenever you need to integrate extended functionality into a single package, SiPs offer a number of advantages. The first and most obvious is the saving of space. Mobile phone manufacturers, for example, are willing to accept the extra cost of a PoP or stacked-die SiP that combines the phone’s baseband processor and memory, because they simply do not have enough room inside the phone to mount these chips alongside each other on a PCB.
Another advantage of SiPs for RF applications is performance. Figure 3 shows critical RF passives stacked to form a SiP, which can greatly reduce parasitics and add as much as 2dB additional sensitivity into a RF receiver chain. For customers, that means better reception in their products, resulting in fewer field returns and a better brand image.
Another potential advantage of a SiP is its shorter development time. Large SoCs can take many tens of man-years to design, particularly if they contain nondigital functionality such as RF circuitry that is not well supported by EDA tools. Partitioning the RF part out of the SoC and implementing it in a more mature and dedicated RF process technology can significantly shorten the design time and thus allow for faster time-to-market. If the market is large enough and long-lived enough, designers can then continue to develop a SoC version of the SiP in order to cost-down the system in line with customer demands.
However, whether it’s increased integration density, superior performance, or shorter time-to-market, the reasons for going to a SiP solution must be compelling enough to overcome challenges. One of the most often cited challenges is the known-good die (KGD) requirement.
 Figure 3. GSM module from NXP integrates critical RF passive components into the SiP, and achieve 2 dB signal sensitivity improvement. |
If you implement a system as a collection of ICs and discrete components mounted onto a conventional substrate, such as a PCB, you can relatively easily identify and replace any component that turns out to be faulty. If you embed all these components into a SiP, you cannot. This means that if an assembled SiP turns out to be faulty, all the added value built into it is lost. The best way to minimize this problem is to 100% pre-test all the components of the SiP before assembly, but this places a much greater burden on wafer probing and testing than would be the case for conventional IC fabrication and packaging.
KGD issues in SiP production is one of the main reasons why the PoP style of SiP has been introduced for applications such as processor/DRAM combinations. Both the processor and the DRAM can exist in a testable packaged form before the two individual packages are fused together into a single PoP style SiP.
Conclusion
Where there is no compelling reason to move to a SiP, it is clear that SoCs will continue to remain the core of many systems. However, if there is a compelling reason to do so, SiPs will continue to absorb more of the system around them, ultimately incorporating nonelectrical functionality into the package so that they steadily move towards true system solutions. Thus, SoC and SiP will continue to coexist for many years, and semiconductor manufacturers must be able to provide a range of solutions: a naked die for supply to a module maker, a conventional packaged IC, or a complete ready-to-use plug-and-play SiP solution.
Alain Rougier is senior director and SIP program manager at NXP Semiconductors, Caen Cedex, France; ph 33/0-23145-6007, e-mail [email protected].
Eef Bagerman is senior director, IMO-backend innovation, at NXP Semiconductors, Nijmegen, The Netherlands.