A methodology and system for automatic litho hot-spot repair
10/01/2007
Executive OVERVIEW
This paper describes a design-for-manufacturing (DFM) methodology and system for optimizing layouts to eliminate hot spots. This approach takes into account actual foundry information, including defect data, fab-specific optical and litho settings, and simple and composite design rules. The automated layout optimization uses a 2D layout manipulation engine that is dynamically aware with respect to cost and violation of design rules. The outcome is a yield-enhanced GDSII layout that is printable and as insensitive to process variations as possible.
As technology migrates from 90nm to 65nm and 45nm, it is increasingly difficult to achieve fast yield ramp due to random defects, process variations, systematic yield problems, and other limitations referred to as DFM issues. At 90nm and finer process nodes, these problems often appear as layout hot spots.
 Figure 1. Yield issues in IC design [6]. (Source: Kohyama/Toshiba) |
To avoid downstream yield and manufacturing problems relating to layout hot spots, it is imperative that hot spots are addressed at every stage of the design-to-manufacturing flow, starting from the development of the library elements to mask data preparation (MDP), which is the last data processing step before reticle generation [1]. If hot spots are not addressed at each stage of the flow, it is quite common to have hundreds of thousands of them in a typical 65nm SOC design [2].
In the world of IC design, the wavelength of steppers used in lithography has not kept pace with the progress of semiconductor processing. Lithographers know the wavelength of the light source is much greater than the minimum dimensions needed on a wafer, resulting in qualitative defects in layout that lead to catastrophic or parametric yield loss: lithography hot spots. Room to maneuver is very small, making it difficult to produce well-defined wafer patterns [3]. Problems such as depth-of-focus and misalignment exacerbate the situation, making lithography the main component of feature-limited yield (Fig. 1), and a major contributor to yield loss-up to 40% of the overall yield loss [4] in some cases.
Hot spots and yield-loss mechanisms
The factors that accelerate the creation of hot spots are the lithography gap and the tightly packed, minimum dimension nature of layout. Such a layout is typically seen inside cells on critical layers-such as poly, metal-1, contact, and diffusion layers-where most hot spots occur. The lithography-induced hot spots manifest themselves in layout as defects and are best detected by analyzing a layout for problems related to common yield-loss mechanisms: printability; contact/via cover margin; and gate uniformity. Another common layout-related yield-loss mechanism that amplifies these hot spots is random defects.
The hot spots due to printability, contact/via cover margin, and gate uniformity (gate variation) are all detected by measuring the critical dimension (CD) and edge placement errors (EPE) between the simulated contour and the corresponding target layout. For example, driven by subwavelength effects, an improper contact/via cover margin may result in an open or a high resistance contact or via, in turn leading to a catastrophic or parametric failure.
 Figure 2. Examples of gate variation in gate height (W) and length (L). |
Again, due to the subwavelength factor, gate variation is a common and growing problem at 65nm and below [5]. Gate uniformity (Fig. 2) effects are detected by measuring the difference between the simulated contour and the corresponding target layout. Gate variations (variations in W and L, as shown in Fig. 2) impact leakage power and device timing, producing parametric yield problems.
Since each cell is instantiated ≥1000× in a typical 65nm design, not addressing the hot spots at the cell layout level would lead to a thousand-fold or more proliferation of hot spots at the chip assembly (place and route) or MDP stage of a design. In addition, a certain number of RET-induced hot spots pop up at the post-RET stage that need attention. How are these addressed today?
There are point tools to detect each type of hot spot. Layout issues such as random defects can be automatically repaired using wire spreading and contact/via doubling tools. Other hot spots are fixed manually. The biggest drawbacks to this method of repair are:
- lack of trade-off between the various types of hot spots that plague a design, and
- inability to make automated repairs.
Since not all hot spots have the same impact on yield, trade-off is critical to determining which hot spots to target for repair to get the maximum return on yield. Automation enhances productivity and reduces the risk of errors inherent in the manual approach.
 Figure 3. Phases of SOC DFM methodology. |
Methodology for hot-spot removal
The typical phases in a SOC design methodology (Fig. 3) are infrastructure, design implementation, and MDP. At subwavelength process nodes, the best-practice methodology is to address hot spots and other layout-related yield limiters in a design-to-manufacturing flow at several stages:
- the cell/IP layout level for critical layers;
- the place and route stage for interconnect layers for a given IC design (for random defects and chemical mechanical polishing effects); and
- the post-RET MDP stage to take care of RET-induced hot spots.
Automatic repair/optimization
Layout yield-limiters are not created equal-their probabilities of failure vary. An automatic repair and optimization solution to address these layout yield-limiters should take the following actions:
- Address yield limiters as early as possible in the design-to-manufacturing flow.
- Provide a rating system to determine which hot spots to target based on their individual impact to the yield of a chip.
- Perform trade-off analysis to objectively compare various types of layout yield limiters.
- Target the high-impact layout yield limiters (fix 20% of the limiters to get 80% of the benefit).
- Repair the targeted hot spots as a whole.
- Produce a layout that is correct by construction.
The Takumi Enhance system inputs GDSII data (describing standard cells, for example) along with data about hot spots and manufacturing technology and produces a new yield-optimized GDSII layout. Besides optimizing for yield and reducing gate leakage power, it can assist library migration to finer geometries and among fabs.
 Figure 4. A representative sample of the results from the application of the automatic repair/optimization of layout. |
Results
A representative sample of the results from the application of the automatic repair/optimization of layout is illustrated in Fig. 4, which shows the before and after optimization of a cell layout. The issue was that the poly segment was not violating any design rules under normal conditions, but under a defocus condition it was too close, forcing an extra spacing between the poly and the contact. This simple spacing requirement caused 2D changes to the layout across multiple layers, along with shifts and rotation of various layers. All of these took less than a minute to accomplish with the automated system, which would have otherwise taken a few days.
The system also analyzed Renesas Technology’s standard cell library for a 65nm process node. Since the potential impact of each hot spot on yield varies widely, the system trades off the low “cost” yield issues for the higher “cost” ones, resulting in the best possible optimization in terms of failure rate values. For example, yield issues that arise from single contacts, random defects, and contact cover margin were considered as low cost items for trade-off in the optimization process. Renesas assigned higher cost for gate height variation and contrast-related yield issues on metal-1, poly, and diffusion. The resulting optimization on the entire 500-cell library traded off gate variation and contrast against all other yield-loss issues, reducing the number of hot spots by 12.5 percent and the overall failure rate by 29.7 percent. Some specific hot-spot types, such as gate height variation (W in Fig. 2), were reduced by >70 percent (see table).
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Conclusion
As long as photolithography is the dominant process for semiconductor manufacturing, hot spots are here to stay. Hot spots complement other layout-related yield-loss mechanisms to increase the possibility of device failure both from catastrophic and parametric points of view. Hot spots must also be addressed at the cell level, otherwise there will be too many hot spots at the chip level. In order to perform objective tradeoff analysis between different types of hot spots and to target the right ones, they must be rated using a common measure.
For every change the hot spot repair mechanism performs, it must at a minimum be dynamically aware of the impact to cost and design rule requirements. The layout optimization must be automated and made extensible for future process nodes, thereby protecting a user’s investment. Finally, the system must deliver higher yielding layout that is printable and as insensitive to process variations as possible.
References
- Aaron Hand, “Litho Simulation Enables the Leading Edge,” Semiconductor International, 2006.
- S. Inoue, S. Kobayashi, S. Kyoh, T. Kotani, T. Inazu, A. Ikeuchi, et al, “Development of Hot Spot Fixer,” Proc. SPIE, Vol. 6156, 2006.
- Barry Lieberman, “Maskmaking Tutorial,” (ftp://download.intel.com
esearch/silicon/Lieberman.pdf), Intel Corp. - Peter G. Feist, “Shedding More Light on DFM signoff,” ED Online, Feb. 10, 2006.
- Peter Rabkin, “DFM for Advanced Technology Nodes: Fabless View,” Future Fab International, Vol. 20, 2006.
- Mark R. Pinto, “Growth through Nanoelectronics Leadership,” Applied Materials, SEMICON West, July 12, 2005..
Tom Wong received his BSEE and MSEE from the U. of Wisconsin and is VP of marketing at Takumi Technology Corp. USA, 150 Mathilda Place, Suite 288, Sunnyvale, CA 94086, United States; ph 408/503-8889; email [email protected].
Ravi Ravikumar received his BE from the U. of Madras, India, and his MSEE from the Florida Institute of Technology. He is the director of marketing at Takumi Technology Corp. USA.