Accelerating semiconductor R&D with combinatorial technology
10/01/2007
EXECUTIVE OVERVIEW
High productivity combinatorial methods have been integrated with characterization systems and an informatics infrastructure to rapidly accelerate the pace of materials-based R&D. Massively parallel screening of chemistry matrices is done on silicon coupons, and sequential screening allows for proof-of-concept in a matter of days. Custom hardware to isolate and process up to 28 isolated sites in parallel across a 300mm wafer allows for rapid process integration. This methodology was used to develop an improved post-Cu CMP wet-clean formulation at the 45nm node in just 3.5 weeks, using a total of only 16 wafers.
Over the past 40 years, CMOS integrated circuit (IC) performance has been driven primarily through scaling-shrinking the chips’ features. However, 50% of performance improvements at the 90nm technology node were driven by new materials, processes, and device architectures [1]. It is estimated that these new factors will account for an even higher percentage going forward, resulting in significantly increased complexity, risk, and costs associated with semiconductor R&D. R&D spending is expected to grow exponentially from $45B in 2006 to nearly $100B in 2010 [2].
Furthermore, the use of high-volume manufacturing tools to conduct R&D for new materials is inefficient, given the costs and time involved in changing chemistries and conditions, and given the frequent use of entire 300mm wafers to generate a single data point. Clearly, there is a need for a major change in the semiconductor R&D process to deliver faster solutions to IC manufacturers’ material, process integration, and device integration challenges.
Intermolecular’s High-Productivity Combinatorial (HPC) methods and systems address the industry’s complex R&D problems by rapidly accelerating the discovery and integration of new materials, new process technologies, and new device structures. HPC technology mitigates risk and complexity, while delivering better answers faster, with a lower R&D cost than conventional approaches.
The key differentiator with this approach is its ability to quickly correlate chemistry to electrical results. In other words, HPC solves R&D problems by going beyond materials science and actually examining the influence of new materials and chemistry formulations on device performance.
Fluids-based combinatorial workflow
The Tempus HPC platform is built on three pillars of processing, characterization, and informatics (Fig. 1).
Massively parallel processing. For the automation and rapid processing of multiple experiments, three fully automated, site-isolated processing tools have been developed:
- F-10, a system for materials discovery, including handling of powders and viscous formulations;
- F-20, for unit process development, including testing on partial-wafer “coupons;” most processing work described in this paper was carried out on the F-20; and
- F-30, for integration and scale-up testing on 200mm and 300mm wafers, with up to 28 isolated sites per 300mm wafer (Fig. 2).
 Figure 1. The Tempus fluids-based HPC platform shows automated and integrated set-up, execution, and analysis. |
Characterization. Fully automated metrology and e-test infrastructure is used to rapidly characterize the physical and electrical performance of developed technologies, throughput-matched to the parallel processing tools.
 Figure 2. A 300mm test wafer processed on the F-30 shows 28 isolated sites that were processed independently. |
Automation and analysis informatics. For experiment design, development operations, and data management, a proprietary informatics infrastructure consists of a comprehensive, secure, web-based system for integrating process and characterization tools into unified R&D workflows.
The F-20 system enables users to conduct experiments without the limitations imposed by wafer cost, metrology bandwidth, and tedious solution preparation. With careful consideration of the screening logic and subsequent workflow design, new formulations can be discovered and optimized in a matter of days, instead of months as is the case with conventional R&D methods.
From a high-level perspective, the F-20 performs two main functions. The first is formulation preparation from base components, using the informatics software to design formulation libraries. Users can quickly define the composition of every site in the library or they can use specialized design of experiments (DOE) software to prepare an experimental design for import. The informatics system then provides an automatic link between the processing conditions and the metrology results.
The second function of the F-20 is to process coupons from a wafer using the previously prepared matrix of formulations. The F-20 reactor can simultaneously process up to 32 site-isolated locations per wafer coupon. A single 300mm wafer can be cleaved to produce six of these coupons, allowing up to 192 unique experiments per wafer with powerful flexibility. Users can control numerous variables, including reaction times, temperature, ambient (air, nitrogen, other), fluid dynamics (static bath, stir rate, etc.), and chemical composition.
Workflow design and screening
Workflow tasks are divided into roughly concurrent primary, secondary, and tertiary screening experiments. In the initial setup of a workflow for a specific development purpose, it is important to characterize the overall screening methodology to prove that the data gathered in early screens is indeed valuable in informing later screens, and to ensure that the results will correlate predictably to those obtained from high-volume manufacturing tools.
The purpose of the primary screen is to use readily available substrates to evaluate a large number of potential candidates. In most workflows, primary screening is performed on blanket substrates. The data collected during primary screening is used not only to rank and select a subset of formulations to carry forward into secondary screening, but also to provide chemical insight into the system and to start developing a self-consistent and predictive model.
In secondary screening, the number of potential chemistries is narrowed significantly, and hence it becomes practical to use more costly substrates to perform more involved characterization for statistically valid results.
At the tertiary screening level, only a small subset of the very best chemistries remain. The risk of ending up with a poor product has largely been eliminated, and it is now appropriate to collect a comprehensive data set from patterned wafers for subsequent correlation to processing results from high-volume manufacturing tools.
Combinatorial R&D of pCMP cleaning chemistry
We used Intermolecular’s Tempus fluids-based HPC workflow in the rapid development of an improved post-Cu chemical mechanical planarization (pCMP) clean process to aid in the transition from the 65nm to the 45nm technology node. Traditionally, pCMP cleaners have relied on surface etching to undercut and lift-off residues [3]. However, this often leads to grain-boundary decoration or selective etching of specific copper grain structures, causing an increase in the Cu roughness that is exacerbated with shrinking device geometries. Increased roughness leads to issues with metrology since killer defects may be lost in the haze. Additionally, electrical performance can be degraded by surface scattering effects from the roughened Cu. We want a pCMP cleaning formulation that effectively removes slurry residue without copper roughness or degraded low-k dielectric material issues.
Primary screening. In the pCMP clean workflow, the primary screening objective was to achieve controlled and uniform copper etching, resulting in a smooth, defect-free surface. This required the use of electrically testable patterned substrates, rather than the more common blanket substrates. Primary screen characterization consisted of measuring the change in serpentine line resistance (an extremely sensitive proxy for copper etch rate) as well as atomic force microscopy (AFM) to determine the roughness of the copper probe pads.
Path-finding DOEs were used first to rapidly screen a wide variety of molecules. In a typical experiment, libraries and experimental parameters are defined off-line and saved to the informatics database. The F-20 pulls chemical composition information from the database and uses it to prepare formulations from the source components. Highly accurate solution dispensing, stirring, and temperature control ensure a precisely defined composition at each location. All the details of the experiment, including a date and time stamp, are recorded back to the database. Once the library is prepared, a coupon is loaded onto the tool, processing parameters are pulled from the database and all formulations are simultaneously transferred to the reactor (Fig. 3). After processing, the sample is loaded into a variety of automated metrology tools (in this case AFM and e-test) that measure and upload relevant data to the informatics database.
The informatics system allows researchers with appropriate access privileges to view and analyze the data in real time. Figure 4a shows an example of AFM results from a path-finding library, where each image corresponds to a unique chemical formulation from a total of 30 experiments, tested with three-fold repetition. Resistance data for the same library are shown in Fig. 4b. The entire experiment, from design to data analysis, was carried out in two days using one wafer. The F-20 makes it easy to rapidly collect many such data sets, and the large volume of data produced is easily stored and analyzed with the informatics system. An HPC workflow’s massively parallel processing, throughput-matched characterization, and informatics system can save substantial R&D time and cost during any wet chemistry development process.
Data analysis from the preceding example revealed a strong correlation between the copper roughness and the copper etch rate. However, a few formulations deviated significantly from this trend line (Fig. 5). Formulations that lie below the trend line (circled in red) exhibit high roughness values relative to their etch rate, and thus tend to remove copper non-uniformly. Formulations above the trend line (circled in green) exhibit the desirable property of an unusually smooth surface, despite removing significant amounts of copper. The informatics analysis immediately revealed that all above-the-line formulations shared one molecule family in common. Subsequent work revolved around optimizing formulations containing this molecule to meet the specifications for line resistance and roughness values at the 45nm node.
Secondary screening. In the case of the pCMP clean workflow, the limiting factor was access to wafers that had been processed on a customer tool using the customer’s slurry, but which had bypassed the customer’s existing pCMP clean. Using these substrates sparingly was a critical factor in the workflow design. Secondary screening also served the purpose of validating the primary screen. When a set of chemistries was run on these dirty wafers, a good correlation was found between cleaning ability and copper etch rate.
With that validation in hand, we re-initiated primary screening and began optimizing a clean formulation based on a lead molecule from the family mentioned above. During optimization, traditional DOE software is typically used to efficiently map the phase space of interest. In this case, a full factorial design was used to simultaneously vary the concentrations of three important chemicals. Next, several of the most promising formulations that showed good correlation and excellent cleaning performance were carried forward to secondary screening.
Pre- and post-clean AFM data were taken for 15 unique solutions, each comprising one slice of the solution phase space mapped with a full factorial DOE. The concentration of one component was varied against the concentration of another component, and between poor cleaning and unacceptably high roughness an optimum formulation was found. This optimized DOE containing 45 unique formulations was performed in 2 days using one-half of a 300mm wafer.
Tertiary screening. The four best formulations from the previous screening stages were compared with the then-existing cleaning solution being used in 65nm high-volume production, to address not only cleaning efficiency and copper roughness but also the influences on low-k dielectric materials, queue time effects, solution shelf-life, and parametric and reliability-based wafer-level electrical performance. This data set assured the customer that risks inherent to scale-up had been minimized and lowered the barrier to getting the new material into high-volume manufacturing.
Different substrates and metrology tools were used to address each of these issues. To evaluate compatibility with low-k dielectrics, blanket wafers coated with a dense low-k film (k = 2.7) were characterized pre- and post-cleaning for thickness (ellipsometry), k value (mercury probe) and contact angle. None of the final formulations were found to degrade the dielectric thickness or k value. Parametric testing on device wafers was carried out to characterize leakage, resistance, and capacitance. These same wafers were used to evaluate reliability using voltage ramp dielectric breakdown. Scanning electron microscopy (SEM) was also used as a final characterization step to verify cleaning and roughness. Figure 6 shows a comparison of the initial formulation, which cleaned well but caused unacceptable roughness, with a newly developed formulation that had both improved cleaning and roughness performance.
 Figure 6. SEM images comparing the roughness of Cu lines cleaned with the old and new formulations. |
Altogether, 1320 experiments and 3630 characterization sets were logged during the course of this pCMP development. Using HPC, this rapid learning was achieved in 3.5 weeks, using a total of 16 wafers and less than $100 in chemical costs. In comparison, a similarly comprehensive data set developed on a conventional tool set would have taken approximately one year to complete, and consumed 1,320 wafers with over $100,000 in chemical costs! This difference is magnified even further with the increasing complexity of development programs that call for many more experiments.
One of the formulations discovered here is currently being scaled up and used for high-volume manufacturing. The HPC workflow provides not just an optimum formulation, but also the ability to map an entire formulation space (Fig. 7). Both copper roughness and resistance change according to the concentrations of three different formulation components. This process window is well defined, and if customer requirements change in the future, the data needed to adjust the formulation already exist in the informatics system.
Conclusion
The conventional approach to semiconductor R&D is increasingly inadequate due to challenges associated with the introduction of new materials and device structures, which are resulting in rapidly increasing complexity, risk, and cost. A high-productivity combinatorial (HPC) fluids-based workflow was used to identify a post-Cu CMP clean alternative for a key customer to address the problem of increased Cu roughness with shrinking device geometry.
Using the HPC workflow, we generated a significant amount of critical physical and electrical device data in a very short time frame and at a fraction of the R&D cost of conventional approaches. Although described here for post-Cu CMP clean, this same workflow can be used for multiple processes, including self-assembly, wet strip, wet clean, wet etch, and electroless deposition.
What sets the HPC approach apart from conventional methodologies is its ability to carry out massively parallel processing, which significantly reduces the execution time for R&D and translates directly into cost-savings for the customer. Faster R&D results also can mean a competitive advantage and higher revenue potential due to the shorter time to market required for new products. Moving forward, we believe that the HPC approach has potential to revolutionize semiconductor R&D.
Acknowledgments
The authors would like to thank Nicole Rutherford, Chi-I Lang, and Gus Pinto of Intermolecular Inc., and Jeff Barnes and Cuong Tran of ATMI Inc. for essential work and valuable discussion. High-Productivity Combinatorial, HPC, and Tempus are trademarks of Intermolecular Inc.
References
- Thomas Teis, “What Will Make for Success-An IDM Perspective,” presented at the Strategic Materials Conference (SMC), Half Moon Bay, CA, Jan. 2006.
- Ron Leckie, “Funding the Future in the Semiconductor Equipment and Materials Industry,” presented at the Industry Strategy Symposium (ISS), Amsterdam, Feb. 2006.
- Todd Buley, et al., “Performing Advanced Post-CMP Cleans to Reduce Copper Defectivity and Surface Roughness,” Micro Magazine, Oct. 2005.
Zachary Fresco received his PhD in chemistry from the U. of California, Berkeley, in 2005 and is a senior staff scientist at Intermolecular Inc.
Arun Karamcheti received his PhD in materials science and engineering from Rensselaer Polytechnic Institute in 2000 and is a senior manager for product marketing at Intermolecular Inc., 2865 Zanker Road, San Jose, CA 95134, United States; e-mail [email protected].
Nikhil Kalyankar received his PhD in chemical engineering from the City U. of New York in 2007 and is a process engineer at Intermolecular Inc.
Peng Zhang received her PhD in chemistry from the U. of Illinois at Urbana-Champaign, and is a R&D manager in the Surface Preparation Technologies Division of ATMI Inc.
Damo Srinivas received his master of science education in materials science from Arizona State U. and is a VP of interconnect technologies at ATMI Inc.