An efficient low-defectivity process for 193nm resist development
10/01/2007
Executive OVERVIEW
Increased lithography cluster tool productivity is required to reduce the cost of ownership (COO) of today’s advanced 193nm processes. Coater/developer systems, which make up one half of a lithography cluster, have multiple process steps. Typically, the overall tool throughput is determined by the longest process stage. However, efforts to reduce process times, especially photoresist development, must be made without impact to critical dimension (CD) uniformity and baseline defect levels. A new developer nozzle hardware and process have been developed and evaluated on multiple 193nm photoresists that significantly decrease process time and chemical consumption.
One of the final steps in a photolithography coater/developer process is the development of exposed photoresist features. Exposed chemically amplified resist becomes developer-soluble via a thermally driven acid catalyzed reaction during the post exposure bake (PEB). Standard processes then create a static puddle with alkaline developer solution to remove the exposed resist, leaving the patterned features behind. This puddle time varies depending on the development rate parameter of the specific resist.
We have found that chemically amplified photoresists, especially those designed for 193nm lithography, have significantly higher dissolution rates than previous diazonaphthoquinone (DNQ)/novolac materials. This enables a new “continuous dynamic dispense” development concept that dramatically shortens the develop process cycle. New hardware and process solutions were designed to maximize the performance of the dynamic process. Key elements of the new process are:
- The impact or contact of the developer is uniform on the resist surface.
- Defects due to slow dissolution and redeposition of dissolved resist components are reduced.
- The process time and the developer consumption are reduced up to 60% over typical common develop processes.
 Figure 1. Develop process DOE plot of mean CD for the new standard and typical common developer processes. |
We have evaluated several elements of the new Tokyo Electron (TEL) resist development hardware and process, focusing on defect levels, process window, and process latitude with several commercially available resists and have compared these results for both the new hardware standard process and a typical common developer process. A design of experiments (DOE) approach has been used for this investigation [1, 2]. This paper presents our evaluation results, which demonstrate a robust process exhibiting good CD control with low defectivity and high productivity. Silicon wafers (300mm) were processed on a TEL Clean Track Lithius lithography track and an ASML 193nm exposure system. Several commercial 193nm resists for dense and isolated line/space, and contact hole applications were used; all were coated on a bottom antireflective coating (BARC) layer. The developer chemistry used was a standard 2.38% TMAH (tetramethylammoniumhydroxide) with surfactant. Defect inspection was done on a bright-field optical inspection tool with defect review on a scanning electron microscope (SEM). Critical dimension mean and 3σ uniformity were measured on a CD-SEM.
Process DOE evaluation
A replicated 23 full factorial randomized design was used for this evaluation. We tested 1) the effect of a 60-sec typical puddle type process vs. the TEL hardware standard (dynamic) process; 2) the addition of a post-develop dispense (PDD) step vs. no PDD step; and 3) developer temperature at 23°C vs. 21.5°C, the standard developer temperature on other TEL tracks. Each factor has a different significance: the typical puddle process mimics the historical development method used on TEL ACT 12 systems; PDDs are often used to reduce patterned defect levels; and developer temperature has a known effect on the dissolution rate curve.
For the experiments, a 1700Å resist film was coated over a 1000Å BARC film on silicon wafers. A focus-exposure dose matrix was processed to determine the best dose and focus for the baseline develop process. All wafers were exposed and developed per the design, and the CD was measured on a CD-SEM using 48 exposure fields/wafer. Tested responses were CD mean and uniformity for an 82nm targeted line/space (L/S) test site.
The effect of the develop process can be seen in a plot of the mean effects for the two processes (Fig. 1). Error bars for the CD mean plot represent 95% confidence intervals. There is a significant shift in mean CD, ~7nm, between the two processes. Statistical DOE analysis suggests that only the develop process type has a significant effect on CD mean, using a significance level (
 Figure 2. Develop process DOE normal probability plot of CD uniformity. No factor significantly impacted CD 3ò. |
Develop time CD mean and process window
Next, the impact of increasing the dwell (center of wafer dispense) time of the new TEL develop process was tested. As in the previous experiment, a 1700Å resist film was coated over a 1000Å BARC film. Multiple wafers were exposed with the test reticle and developed with the dynamic process using increasing dwell times from 3-17 sec in 2-sec intervals. In addition to the previous tested responses of CD mean and uniformity, process window and exposure latitude vs. depth-of-focus (DOF) were also investigated on the same 82nm L/S targeted test site. The dose and focus settings were held constant to test CD mean and varied in matrix form to evaluate process window changes.
For these experiments, 84 exposure sites were measured per wafer. We found that CD decreases with increasing dwell times at a rate of 0.33nm/sec, determined by a least squares linear fit of the data means, with no significant impact on CD uniformity. However, by plotting exposure latitude vs. DOF, we do see a loss in process window with increasing dwell times. Lower dwell times are sufficient to clear this resist and overdevelopment results in a decrease of the exposure process latitude.
193nm resist suite process window evaluation
Process window analysis for two line/space resists, isolated line resists, and contact hole resists was performed. All resists used are commercially available 193nm materials coated over a standard BARC. We compared the new standard dynamic process with the typical common developer process without a PDD step since this factor was determined to be insignificant in the CD mean/uniformity study. A focus exposure matrix, centered at the optimum dose and focus for each resist, was then processed for both develop process types (Fig. 3). While there are subtle differences, the process windows for the supplier’s standard process and the typical common developer process show similar characteristics in exposure latitude vs. DOF behavior.
Full process bright-field investigation of defect levels
To conclude testing of the new developer process, defect levels were compared between the TEL standard process and the typical developer process. Additionally, we looked at the impact of inserting a PDD between the original develop application and rinse steps. We expect the PDD process will help promote the removal of dissolved resist byproducts, thereby reducing the total number of redeposited defects. PDD times were varied from 0 to 1.5 sec in 0.5-sec increments. Each experimental condition was replicated 3× to understand the process and inspection repeatability. The test vehicle was resist coated over a BARC layer on silicon and all wafers were exposed with a product reticle. Defect analysis was based on total counts measured from a bright-field optical detection system. The analysis of variance (ANOVA) performed on the data showed that using a PDD had no significant effect on the defect counts, and the interaction effect between PDD and develop process was statistically insignificant (
 Figure 4. Full process bright-field total defect count comparison between the new standard develop process and the typical developer process. |
Conclusion
We evaluated TEL’s next generation develop hardware and process using both the supplier’s recommended standard dynamic process and a typical developer process. With the new develop method, the total process time can be reduced by up to 60% from the typical common developer process time of 100 sec or more. In addition to the higher throughput, the new develop process consumption per wafer is <60% of typical common developer process consumption. Both benefits help lower the COO of the lithography track.
 Figure 5. Characteristic defect imaged by SEM on wafers processed with the new standard process for the new hardware |
Full process defect evaluation shows the new hardware and process to be a low defect development solution. While CD mean is dependent on nozzle center reside time, the across-wafer CD uniformity is relatively stable. Although process window loss was seen with increasing center dispense time, short dispense times were sufficient to clear the exposed resist features. Also noted was a dose increase of 4-12% for the TEL standard process vs. the typical developer process. In conclusion, the new hardware and process were found to offer a stable and robust technique for imaged resist development.
Acknowledgments
The authors would like to thank James Kozielski, Steve Schneider, Patrick Lindo, Adam Walton, and Jim Doran for their valuable assistance with CD-SEM measurements. TEL Clean Track Lithius and ACT 12 are trademarks of TEL.
References
- George E.P. Box, William Hunter, J. Stuart Hunter, Statistics for Experimenters, John Wiley & Sons Inc., 1978.
- Douglas C. Montgomery, Design and Analysis of Experiments, 5th Ed., John Wiley & Sons Inc., 2001.
George Mack received his bachelors from the Metropolitan State College of Denver and is advisory engineer at IBM Corp., Rte. 52, Hopewell Junction, NY 12533; ph 845/892-3738, e-mail [email protected].
Jeffrey Bright received his degree in computer science from Dutchess Community College and is a senior process technician at IBM Corp.
Tom Winter received his bachelors in electrical engineering from Northeastern U. and is an applications engineering manager at TEL America, Hopewell Junction, NY; e-mail [email protected].
Kenichi Ueda received his bachelors in mechanical systems engineering from Miyazaki U. and is a process engineer at TEL America.
Steven Consiglio received his PhD in nanoscience from the U. of Albany-SUNY and is a process engineer at TEL Technology Center America, Albany, NY.