450mm wafers: How to scratch that seven-year itch
09/01/2007
Every seven years or so the semiconductor industry shifts to a larger wafer size. Analysis shows that the economic gain from continually shrinking circuit features begins to run out of steam in that time frame, and chipmakers get a seven-year itch to move to larger wafers. The last shift, from 200mm to 300mm, more than doubled the number of chips that could be pumped out of a wafer processing plant. In addition to that, yields have also gotten better for many chipmakers, due to improved process tools, metrology, design automation, and yield analysis methods. So chipmakers can get more than 2.5× good chips per wafer in many cases.
While Intel provided financial help for the shift to 150mm wafers, and IBM stepped in to help finance 200mm tool development, the toolmakers themselves had to pick up the much higher tab for developing 300mm tools-twice, in fact, because a slowdown delayed the transition. Ouch! Unfortunately, the payoff has been very different for chipmakers and tool vendors. Semiconductor companies improved margins and reaped healthy profits from the shift, while some tool companies failed or were acquired and others struggled to pay off the huge R&D costs.
Now consumerization is eating into chipmakers’ margins. The cost of developing new chips is escalating and fast-changing consumer taste means shorter life cycles to pay for costly redesigns. While circuit shrinks and productivity improvements may help the bottom line for awhile, IC producers can see a potential need for another wafer size shift ahead-maybe sooner rather than later. With growing process complexity, it may take years for the whole infrastructure to be ready for another transition, so some of them are urging a start toward 450mm right now.
Not surprisingly, the response of the toolmakers to a plan for another wafer size change is tepid. At SEMICON West, Stan Myers, SEMI CEO, summed up the situation as seen by the tool vendors, saying that huge benefits still remain to be gained by improving 300mm productivity under International Sematech Manufacturing Initiative’s (ISMI) 300mm Prime program.
“Only after these gains does it make sense to go to a larger wafer size, perhaps by 2020 or even later,” Myers said, adding that there is no consensus among chipmakers that another size increase is needed. He also pointed out that strain engineering may be an interim solution for higher performance, and some alternate materials might emerge for future wafers.
Scott Kramer, director of ISMI, disagrees. While cycle time can be improved for 300mm tools, perhaps up to 50%, ISMI studies show that only a small cost reduction, perhaps 5-10%, is feasible, far short of the 30% target. As a result, Kramer’s calculations show the industry will face a $150 billion productivity gap by 2013 if there is no wafer size change. Advancing technology is requiring more sophisticated tools, and depreciation is 85% of total wafer cost, he said.
Tom Abell, a Sematech assignee from Intel who is doing fab studies to determine whether a 450mm shift should be delayed or accelerated, says that since many 300mm tool design decisions were made in the mid-90s before the rapid rise of foundries, they favor high-volume, low-mix (HVLM) environments, and much of the 300mm Prime work is aimed at improving tools and factory systems for high-mix, low-volume (HMLV) fabs. Having gone through two size transitions, he believes work toward 450mm must start now.
Thus, ISMI, which includes 14 chipmakers across the globe, is initiating work on a Next Generation Factory Vision, doing simulations, and planning for availability of 450mm silicon wafers.
The question is: who is going to pay for the tool and process development? Toolmakers say: “Show me the money.” Chipmakers say: “We are the customers.”
Despite all the posturing, economics will decide the issue. If the chipmakers want to be ready for 450mm-and the whole infrastructure must be ready before the shift can take place-they need to contribute major financing for the R&D. This might happen through joint efforts between SEMI, Sematech, and other consortia around the world. Joint programs in development fabs with varying contributions from participants are now common. If Intel and Samsung, as the biggest large-volume chip producers, stand to gain the most, they may have to pay a larger share. If tools are to be flexible for HMLV product lines, foundries will have to pay their share as well. Toolmakers will have to come up with suitable platforms and commit engineers to such a project to make it work.
Open dialogue is a good sign. Good faith negotiations should lead to workable solutions if the need is real.
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Robert Haavind
Editorial Director