Technology news

09/01/2007

Big push coming on two routes to 3D

Three-dimensional (3D) chip packaging using through-silicon vias (TSV) will sweep across the industry over the next 3-5 years, enabling very compact packaging with much better performance, based on presentations and discussions at SEMICON West. Many chipmaker roadmaps include 3D as an interim step from the 45nm to the 32nm node, sources said.

There are two main routes to this 3D future, according to consultant Neil Moskowitz of Chip Connections Consulting Inc., at a SEMATECH-organized session. One is based on current system-in-package (SiP) multichip modules but without the wire bonding. The second is a fab-like-and thus more complex-approach using wafer-to-wafer, die-to-wafer, or die-to-die bonding. Both eliminate wire bonding.

The first approach lends itself to memory chips, he explained. Samsung, for example, laser-drills holes through pads to make contacts. Conductive inks between regular rows and columns provide internal traces. Vertical Circuits Inc. uses printed traces on the edge of stacks as well, he said. Pad extensions can be used with suitable isolation.

The fab-like approach allows heterogeneous chip stacks with a goal of exceeding 10,000 I/O per die to improve device electrical performance, according to Moskowitz. An Intel microprocessor would now require 10,000 bumps, he explained (roughly 9000 for power and ground). This is becoming too dense for today’s chip-scale packaging. Going 3D will also improve electrical performance. Fab processes take a lot of non-recurring engineering (NRE) costs, he said, because of chip diversity. The cost has limited this approach to premium applications, such as edge servers and medical devices. There is great appeal, though, for much wider application, eliminating the need to put microprocessors, SRAMs, and other functions that require different processes onto the same chip. Moskowitz sees very compact circuit cubes in the future, despite many hurdles to achieve this form factor, including a lack of infrastructure, and potential testing and thermal problems.

Moskowitz sees the evolution coming in three phases. Phase I will include developments such as Samsung’s H stack and multilayer ICs, such as flash memory, at the wafer level. Conductive pastes may be used in some cases. Phase II involves surface-to-surface bonding, which would offer big performance gains for applications such as cell phones. Compressible bumps don’t have to be of uniform height, and gold bumps don’t require flux. Surface bump pitches might eventually reach 5µm, he said.

Phase III is a move to system-on-silicon. A microprocessor die, for example, might have face-down chips bonded to it for memory, graphics, and other functions, Moskowitz said. One approach would be to put vias through a passive silicon interposer chip, with active circuit chips face-down on either side. Cooling fluid might run through microchannels in the interposer. He sees this approach being used 3-5 years from now as the pressure builds to move from 45nm to 32nm. The ability of a small multidie package to act like a single die will make the 3D circuit cube approach very appealing.

While wafer-to-wafer bonding might promise cost advantages, the problem will be with bad die on one wafer or the other. This approach might work best for flash, Moskowitz suggested, due to redundancy. Flash die with only 5% good cells can theoretically be used for wafer stacking, because the flash controller can “skip” the bad cells, he explained. In die-to-die bonding, few die will be done as direct flip-chip, he said. It is more likely that a redistribution layer would add bumps to a regular die.

Sharath Hosali of SEMATECH said that his group has development cost models for 3D approaches. Each chipmaker has its own roadmap for TSVs, he said, and they are all very product-specific. Wafer-to-wafer bonding will be for high-end chips only, where all die on both wafers are the same size and yield is very high.

Chip-to-wafer bonding allows varying chip size, and there is a tradeoff between alignment time and accuracy. Vias may be put in before or after processing, but the via-last approach may require drilling through 8-9 layers of interconnect, which could be a big problem. Approaches will include face-to-face, face-to-back, or back-to-face methods.

Hosali described a wide variety of techniques being explored to make vias (etch in parallel or laser-drilled serially up to 10µm deep), passivate and line the holes, metallize, bond, thin, and dice wafers. Vias might be drilled on the front side and the wafer thinned until they come through the back.

Toolmakers are already developing tools suitable for the coming 3D era. Lam Research, for example, is using its experience in etching deep trenches and MEMS devices to offer a via-etch tool. It could adopt the techniques developed to both 200mm and 300mm etch equipment, according to Jackie Seto, managing director, software, MEMS, and packaging. A slightly tapered, very smooth sidewall, will be required. One advantage of the TSV wafer-to-wafer approach is that the chips on each wafer can be smaller, so yield could be high even with a few defective chips. While chipmakers have TSV on their roadmaps, most haven’t worked out integration schemes yet, Seto noted.

A consortium has already formed in the industry for developing a 3D packaging infrastructure, and research funding is steadily increasing. -B.H.

Intevac goes linear with entry into the dielectric etch market

Since its inception in 1991 (via a LBO spin-off from Varian Semi Equip. Assoc.), Intevac Inc. has been focused on magnetic disk media sputtering/coating technology. In recent years, ~40-50 senior level managers and technologists have joined the company from such firms as Applied Materials, Lam, Varian, and Novellus. With a renewed focus, Intevac launched its new Lean Etch tool at SEMICON West, setting its sights on the dielectric etch market.

According to Ian Latchford, marketing director at Intevac, the new platform is a six-chamber tool-three chambers each in two independent banks, with each chamber also independent of the others, and two independent linear robots running lengthwise along the tool. When both banks are fully operational, the tool can achieve total throughput of 200 wafers/hr, he told SST. If one chamber goes down, the chamber can be taken down for service-or, if the end user prefers to take the entire bank down (to do general service), the tool is still able to perform at 100 wafers/hr with the remaining bank. Maintenance personnel can literally walk through the tool in order to perform work, Latchford noted.

The significance of the platform design, according to Kevin Fairbairn, company president and CEO, is that it eliminates the wasted space associated with cluster tool designs. He cited other cluster tool drawbacks such as bottlenecks, and poor service access to process chambers and wafer handling platforms.

The company does not plan on stopping with dielectric etch, nor with future extensions to silicon and metal etch applications. Latchford noted that the new platform is universal and designed for PVD and CVD applications as well. Without being specific, he hinted that some deposition technology might be available by the end of 2008. -D.V.

SURF monitor breaking waves of defects

KLA-Tencor’s Surfscan SP2^XP was released earlier this year (SST April 2007, Tech News, p.29) initially to inspect defects on bare wafers. Now the company has added a SURFmonitor haze analysis capability, an add-on option to either a SP2 or SP2^XP darkfield/brightfield laser scattering surface inspection system, with new image processing algorithms to allow for applications in IC manufacturing.

Since any of the >300 sold SP2-family tools can scan an entire 300mm wafer surface in <1 minute, and since image processing is done by separate dedicated boxes to avoid impeding throughput, there are ubiquitous applications throughout a fab to surf the haze and glean productive information from wafers.

A SURFimage file shows a wafer map with grayscale information for haze. In certain obvious cases, a characteristic signature may be seen in the haze map that indicates the root cause of a problem. For example, radially symmetric defects often track to a wafer chuck (see Figure, panel a), while arcing scratches tend to originate with CMP steps, and some repeating defects may line-up with lithographic stepper shot positions. In such cases the raw SURFimage may be sufficient to point to the problem, but in other cases the signal of interest is still a bit lost in the noise. Streaks of chemical residues from a wet clean tool may be present on a wafer but difficult to resolve without further image processing (panel b).

To efficiently convert the image of a haze map into the “productive” information of a root-cause diagnosis, image filtering and processing is done by a SURFengine image computer located next to the SP2 tool, which recognizes and extracts the defects of interest, generates alarms, sorts and filters defects by type, and passes this information on to a yield management system for SPC charting and further troubleshooting. The SURFengine boxes in the fab are networked together using a remote SURFstation, for engineering analysis, access to x/y coordinates for DR-SEM and troubleshooting, and recipe writing. The raw haze maps are archived in the SURFengine for up to one year, allowing for retroactive data mining and trend tracking.

KLA-Tencor is positioning this new capability as a hybrid between defect inspection and metrology, and indeed it seems to overlap with both. In terms of extracting metrology information, the SURFmonitor has already demonstrated excellent correlation between haze maps and surface roughness, grain size, and thickness for certain thin films. The company claims >95% (typically 98%-99%) correlation between haze maps and atomic force microscopy (AFM) for grain-size measurements of hemispherical-grain poly, copper, and tungsten.

“Many 45nm and 32nm fabs are interested in monitoring surface morphology for a variety of applications,” explained Rahul Bammi, senior director of marketing at KLA-Tencor. For example, CMP processes require expensive consumables-sets, and having some capability to provide rapid-response to excursions allows for increased use of consumables without risking excessive work-in-progress. Being able to rapidly extract the signatures for CMP scratches or jitter from haze maps allows the CMP process to be run with longer time on a given consumables-set.

a) The clear signature of a W CVD chuck as haze contrast. b) A processed haze map after a wet-clean step. (Source: KLA-Tencor Corp.)Click here to enlarge image

In developing immersion lithography processes, a characteristic residue watermark has been found that is so thin it is undetectable by an ellipsometer. The processed haze map could detect these “sub-threshold” defects on blanket test wafers, and those locations correlated perfectly with brightfield defect data from product wafers. “This eliminates accidents before they happen,” Bammi noted.

Another example of novel productive-information generated by SURFmonitor is the ability to detect pinholes in grown gate-oxide. One fab customer had experienced gate-oxide breakdowns as seen by electrical test results that tracked to DR-SEM pin holes in the oxide, yet they had no in-line method to detect these pin-holes. The SURFmonitor results after image processing correlated to the pin-holes detected by electrical test.

Overall, this new capability provides fundamentally new knowledge about what is happening on an advanced silicon wafer during manufacturing-and since knowledge is power, this adds tremendous power to what used to be “just defect inspection.” -E.K.