Enabling yield at 45nm: Managing process variability
09/01/2007
With the industry moving toward manufacturing at the 45nm half-pitch, new strategies that go beyond the Bossung curve, first introduced in 1977, are required to ensure manufacturability. The issues emerging now are that the time to reach final yield has been growing with each generation, and the plateau yield value at maturity has been steadily declining, with systematic pattern-related defects primarily responsible on both accounts. Also, the number of variables influencing the fidelity of pattern transfer is increasing, and the interaction between them is leading to vanishingly small or negative margins.
Process variability can no longer be addressed solely by continuous improvement in fab equipment control nor by the assumption that model-based OPC will fix all systematic pattern-dependent errors at the center of the process window. Instead, a three-tiered approach is needed to mitigate the impact of residual fab process variability.
First, the members of the design community must have the ability to anticipate the impact of fab variability on physical designs. Traditional rule-based geometric design rule checks define the manufacturing-allowed layout topologies. However, low k1 lithography has driven an explosion in the number of rules required to describe the myriad disallowed layout configurations. Model-based tools can account for variability in the lithographic process inputs during the design phase.
Designers can access so-called “process variability bands” that describe the sensitivity of the layout to manufacturing variations, and allow for optimization of layouts for manufacturing robustness. Using these techniques, designs can have quantitative manufacturability indices to enable relative yield prediction prior to production. Pushing process variability awareness upstream to designers leads to fewer systematic yield-limiting layout configurations in the fab.
Second, process-aware models need to be utilized during the mask data preparation stage. Model-based OPC has been used in recent years to correct for systematic proximity printing errors manifest at optimum exposure conditions. Continuous improvement in the accuracy of lithography models is enabling higher accuracy in predicting CDs for different locations of the Bossung curve.
Today’s patterning models clearly bring into focus the systematic impact of random and concurrent fab process variability. In addition, a new breed of intelligent OPC algorithms is emerging that comprehends multilayer design intent and can optimize corrections by balancing the differing impact of process variability on different features. For instance, corrections can be applied to gate regions based upon a best focus model, such that minimum deviations from the gate CD target are realized in manufacturing. The corrections to interconnect poly contact landing pads, however, might be made to maximize contact enclosure, and minimize poly-poly bridging for slight defocus or underexposure.
Third, with process-aware models, the impact of manufacturing variability on the final OPC-corrected layout can be anticipated. It is important to verify the design as “manufacturing-robust” prior to committing masks to production, so that variability-induced “hot spots” can be identified for iterative correction, or passed to the final key element for coping with variability-design-based metrology (DBM). Historically, in-fab SEM inspections with high spatial resolution have been performed with extremely sparse sampling, due to cycle time constraints. Typically, some representative simple test structures are placed in a scribeline to act as process health monitors. With DBM, however, the fab inspection equipment can be judiciously targeted to yield-relevant locations.
Recent methodology and tool developments build upon the foundation of the Bossung curve, making it possible to account for, correct for, and characterize variability through virtual manufacturing. This capability elucidates the intersection between process variability and specific designs, providing opportunities for significant value-add throughout the design to silicon flow.
John Sturtevant is director of RET technology support for the Manufacturing Integration Initiative, Design to Silicon Div., Mentor Graphics Corp., 8005 SW Boeckman Rd., Wilsonville, OR 97070, United States; e-mail [email protected].
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John Sturtevant, Mentor Graphics Corp., San Jose, CA, United States