Issue



Strain-enhanced scaling of HK+MG CMOSFETs


09/01/2007







As CMOS devices scale down below L = 100nm, improvements in performance deviate from conventional scaling rules mainly because of carrier velocity saturation and limited gate oxide scaling. To overcome these issues and continue to improve performance with scaling, various process-induced strain techniques have been developed and employed in working devices. Several techniques have been reported to improve carrier mobility by altering the energy band structure in the channel region through strain induced by adjacent materials. This so-called “strain-enhanced scaling” has provided another tool to boost the performance of nanoscale CMOS devices and has evolved through a couple of technology generations.

Evolution of strain-enhanced scaling

Since the 90nm node, strain-enhanced CMOS scaling has been very important in continuing Moore’s Law [1, 2]. Mechanical strain modifies the crystallographic geometry in the channel, modulating carrier properties by modifying energy band structure. Strain in the channel region affects the effective mass of carriers and therefore their mobility. Strain affects not only the effective mass of the carrier, but also the backscattering rate (r) at the carrier injection point from the source side [3, 4]. Strain in the channel has been shown to reduce effective mass to increase the injection velocity (v) and ballistic efficiency (B) of the carrier transport by reducing the r [3]. As shown in Eqn. 1 in Fig. 1, increasing v and B raises the saturation drain current.

There are generally two methods to induce strain in the channel region: biaxial strain and uniaxial strain. Biaxial strain is also referred to as global strain mainly from substrate engineering, such as strained Si on SiGe or strained Si on insulator [5]. Biaxial strain using substrate engineering has been extensively studied, but not yet implemented in high volume manufacturing because integration is impeded by the large number of defects at the interface between the material boundaries in the substrate that cause global strain.

Uniaxial strain is generated by local structural elements of the MOSFET near the channel region, such as shallow trench isolation (STI), silicide, the contact etch stop layer (CESL), and source and drain (S/D) [6]. Since these process modules that cause uniaxial strain are part of CMOS processes, uniaxial strain is also referred to as PIS. Owing to the relative ease of integrating PIS modules in conventional CMOS processes, strain enhanced scaling has relied on the development of new advanced methods of PIS.


Figure 1. Illustration of carrier injection at the edge of the channel at the source side flowing into the drain. Equation 1 describes the saturation drain current with injection velocity (Eqn. 2) and ballistic efficiency (Eqn. 3).
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Hf-based high-k was considered to degrade carrier mobility because of transient charge trapping and/or soft optical phonon interactions with the wave function of the carrier in the channel [7, 8]. Recent advancements in high-k technology reveal that controlling the thickness and morphology of the high-k along with using a metal gate has appropriately resolved the mobility degradation issues with high k [9, 10].


Figure 2. Principles of wafer bowing measurement using the reflection angle of an incident laser scan on the film. The method to extract the stress of the film using wafer bowing is described in Eqn. 4.
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Lately, it also has been reported that metal gate on top of high-k causes strain in the FinFET channel, thereby improving carrier mobility if employed appropriately [11]. As HK+MG are the key technologies of choice for 45nm and below, it is important to evaluate the possibility of using the layer as an additional source of PIS. In addition, the interaction of existing PIS techniques, such as stressed CESL and SiGe S/D, with the metal/high-k layer in the gate must be investigated.

Stress measurement in thin films

Measurement of stress in thin film generally begins by preparing a blanket wafer with a known initial wafer bow. After depositing a thin film on the blanket wafer, the wafer bowing is measured again to see if it is changed by the deposition. The stress of the film then can be calculated by Stoney’s equation (Eqn. 4 in Fig. 2) using the difference in the amount of wafer bowing before and after film deposition [12].


Figure 3. Illustration of stress in the film and corresponding induced strain in the substrate: a) tensile stress in the film; b) compressive stress in the film.
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Wafer bowing is measured using the reflection angle of the incident laser on the film as illustrated in Fig. 2. The laser is incident to the film with a known incident angle, and the reflection angle of the light is measured using a location-sensitive photo diode. The change in reflection angle with respect to laser scan distance yields the curvature of the wafer.

The sign of stress (i.e., tensile or compressive) is determined by the shape of the wafer bow or curvature. When the film is stretched to fit the substrate, the film’s tensile stress causes compressive strain on the underlying substrate (Fig. 3a). When the substrate is allowed to bend, the film makes the wafer concave. When the film is squeezed to fit the substrate, the film has a compressive strain and the substrate is strained in the tensile mode (Fig. 3b); the wafer is then convex when the substrate is released.

In the gate-first metal/high-k integration approach [13], a thin metal gate (3~20nm) on top of high-k dielectric is usually capped with a conventional poly gate due to the ease of integration and gate profile control. Even though the metal gate is rather thin, the stress level could be very high depending on the material and preparation method, as shown in the table. In addition, the proximity of the metal gate to the channel region could enhance the effect of PIS on carrier mobility. Note too, that the stress of the metal gate film modulates with film thickness.

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Figure 4 shows stress of the atomic layer deposited (ALD) TiN film with respect to thickness. The stress of the film changes abruptly at the beginning, but gets shallower as the film becomes thicker. TiN is a representative mid-gap metal gate that is thermally stable with Hf-based high-k and poly Si.

Not only does mechanical stress change with TiN thickness, the effective work function (EWF) of the film also tends to change with thickness. As the TiN becomes thicker, the EWF also increases, presumably due to compositional change in the film [14]. Because EWF modulates according to the thickness of the material, an attempt has been made to use the metal gate for ultra-thin substrate technology to tune n- and pMOS threshold voltage (V) using two different TiN thicknesses on n- and pMOSFETs [15]. The thicker TiN layer has a more tensile stress in the film, thus causing a more compressive strain on the channel, which is favorable for improved hole mobility.


Figure 4. Mechanical stress of ALD TiN film with respect to thickness. As TiN gets thicker, the film becomes more tensile, inducing more compressive strain in the underlying substrate, if used as a metal gate.
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A thick TiN metal gate with a higher EWF and greater tensile stress (i.e., more compressive strain in the channel) can be used to obtain low V and high performance pMOSFETs. nMOSFETs can also benefit from thin TiN metal gate because of the low EWF and greater compressive stress in the film. Strain induced in the channel from the metal gate indeed improves MOSFET performance as shown in Fig. 5.


Figure 5. Ion-Ioff characteristics of a a) nMOSFET and b) pMOSFET with different TiN thicknesses and contact etch stop layers (CESL) of different stress levels. N-CESL, T-CESL, and C-CESL stand for neutral stress, tensile stress, and compressive stress, respectively.
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For the nMOSFET (Fig. 5a), when thin TiN metal gate is used, Ion current improves ~12% compared to devices with thick TiN gate. When tensile CESL is used, an additional 16% Ion improvement is observed. For the pMOSFET (Fig. 5b), when the TiN metal gate becomes thicker, the Ion current increases by 17% and sees an additional 19% improvement with compressive CESL. The additional performance improvement with stressed CESL indicates that the metal gate strain is added to the CESL strain, similar to other PIS techniques.

Conclusion

Incorporating a metal gate and high k into the CMOS process could allow another dimension to the ever-advancing PIS technique, as the metal gate could induce additional strain in the channel, which is added to other strain-enhanced performance improvements. The strain from the metal gate can be tailored by composition, deposition method, and film thickness among other things. It is important to co-optimize the effective work function and metal gate-induced strain simultaneously to achieve the target V and high performance at the same time.

References

  1. S.E. Thompson, S. Guangyu, “Strained Si and the Future Direction of CMOS,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA) pp. 46−47, 2006.
  2. C. Ortolland, S. Orain, et al., “Electrical Characterization and Mechanical Modeling of Process-induced Strain in 65nm CMOS Technology,” Proc. of the 34th European Solid-State Device Research Conf. (ESSDERC), pp. 137−140, 2004.
  3. L. Hong-Nien, et al., “The Impact of Uniaxial Strain Engineering on Channel Backscattering in Nanoscale MOSFETs,” Symp. on VLSI Technology, pp. 174−175, 2005.
  4. D.A. Antoniadis, I. Aberg, et al., “Continuous MOSFET Performance Increase with Device Scaling: the Role of Strain and Channel Material Innovations,” IBM Journal of Research and Development, 50(4), pp. 363−376, 2006.
  5. M.V. Fischetti, S. E. Laux, “Band Structure, Deformation Potentials, and Carrier Mobility in Strained Si, Ge, and SiGe Alloys,” Jour. of Applied Physics, 80(4), pp. 2234−2252, 1996.
  6. F. Andrieu, T. Ernst, et al., “In-depth Characterization of the Hole Mobility in 50nm Process-Induced Strained MOSFETs,” IEEE Electron Device Letters 26(10), pp. 755−757, 2005.
  7. C.Y. Kang, J.C. Lee, et al., “Charge-trapping Effects in HfSiON Dielectrics on the Ring Oscillator Circuit and the Single-stage Inverter Operation,” International Electron Devices Meeting, pp. 485−488, 2004.
  8. M.V. Fischetti, D.A. Neumayer, et al., “Effective Electron Mobility in Si Inversion Layers in Metal-Oxide-Semiconductor Systems with a High-k Insulator: The Role of Remote Phonon Scattering,” Jour. of Applied Physics, 90(9), pp. 4587−4608, 2001.
  9. S.C. Song, Z. Zhibo, et al., “Highly Manufacturable Advanced Gate-Stack Technology for Sub-45nm Self-Aligned Gate-First CMOSFETs,” Transactions on Electron Devices, 53(5) pp. 979−989, 2006.
  10. R. Chau, S. Datta, et al., “High-k/Metal-gate Stack and its MOSFET Characteristics,” IEEE Electron Device Letters, 25(6), pp. 408−410, 2004.
  11. C.Y. Kang, R. Choi, et al., “A Novel Electrode-induced Strain Engineering for High-performance SOI FinFET Utilizing Si (110) Channel for Both n- and pMOSFETs,” International Electron Devices Meeting (IEDM), 4-4, 2006.
  12. C.A. Klein, “How Accurate are Stoney’s Equation and Recent Modifications,” Jour. of Applied Physics, 88(9), pp. 5487−5489, 2000.
  13. S.C. Song, Z.B. Zhang, et al., “Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration,” Symposium on VLSI Technology, 2-2, 2006.
  14. S.C. Song, et al., “Integration Issues of High-k and Metal Gate into Conventional CMOS Technology,” Thin Solid Films 504(1), pp. 170−173, 2006.
  15. C.Y. Kang, R. Choi, et al., “Effects of ALD TiN Metal Gate Thickness on Metal Gate/High-k Dielectric SOI FinFET Characteristics,” International SOI Conference, pp. 135−136, 2006.

Seung-Chul Song received his BS and MS degrees in materials science and engineering from the U. of Inchon in Korea, and his PhD in electrical and computer engineering from the U. of Texas at Austin. He is project manager in the Front-end Processes (FEP) Division at Sematech in Austin, TX.

Mustafa M. Hussain received his BS in engineering physics and his MSEE from Texas Tech U, and his PhD in electrical engineering from Texas Tech. He works as an integration engineer in the FEP Division at Sematech.

Cynthia Burham is pursuing her PhD degree at the U. of Texas at Austin and is a full-time intern at Sematech.

Chang Seo Park received his BS and MS in ceramic engineering at Yonsei U. in Korea, and received his PhD from the U. of Singapore. He is an engineer in the advanced metal electrode project at Sematech.

Byoung Hun Lee received his BS and his MS in physics from the Korea Advanced Institute of Science and Technology, and his PhD in electrical and computer engineering from the U. of Texas at Austin. He is a manager of the Advanced Gate Stack Program and METS-ECR program in the FEP Division at S, 2706 Montopolis Drive, Austin, TX, 78741, United States; e-mail [email protected].

Rajarao Jammy received his PhD in electrical engineering from Northwestern U. He is an assignee from IBM and a director of the FEP Division at Sematech.