Addressable array technology for systematic yield monitoring at 65nm
09/01/2007
Random yield loss is caused predominantly by process- and equipment-generated particulates, which are monitored in the fab using inline defect-inspection tools. While random limited yields vary by product, they vary in a predictable way according to the widely accepted critical-area model.
Systematic limited yield is, by definition, layout-specific, and is difficult to monitor accurately. Systematic yield loss occurs when a specific feature in the design cannot be robustly reproduced on the wafer-in other words, the feature’s process window (PW) is not large enough to accommodate normal variations in the fab. A unique systematic “feature” might be as simple as the space between two parallel horizontal lines, or the width of a line close to the end of another orthogonal line. The influence of reticle-enhancement technology (RET) such as subresolution assist features (SRAF), coupled with advanced features of the lithographic system (e.g., off-axis illumination), create unique PWs for each feature.
 Figure 1. Average number of design rules by technology node. (Data: Synopsys Inc.) |
As technology nodes scale, RET is needed for more layers and must be made more aggressive. Both trends lead to a rapidly increasing set of yield problems due to systematic effects, with product yields that are dependent on the design, tape-out, mask, and fab. Since each product design contains a unique set of features associated with every electrical net, each product will also have a unique sensitivity to various systematic yield issues. Furthermore, the same product may exhibit different yield signatures in different fabs, due to unavoidable differences in RET, maskmaking, lithographic, or other tools. This fab dependency on systematic yield will become more important as economic realties move the industry toward more affiliated fab ecosystems [1].
In prior technologies, fabs could guide designers away from acute systematic yield limiters by adding design rules. This process of guarding against systematic yield marginalities has been the predominant reason behind the exponentially increasing design-rule count with every new technology generation (Fig. 1), and the commensurate increase in physical verification cycles. Physical verification of 65nm designs, which can require 1000-2000 cluster computer centers, can still take days. However, design rules alone cannot guarantee yield. While feature pitches have been shrinking predictably, the lithographic interaction distance (distance at which proximal features influence the printing of a target feature) has been increasing. In the past, the effects of proximal features extended only to the nearest neighbor features, but today, significant effects come from many more secondary features (Fig. 2). A quick look at Fig. 2 underscores the fact that our technology has outgrown the ability of a rules-based approach to describe it. As shown in the figure, the lithographic interaction radius increases relative to pitch with shrinking technology node due to increasing numerical aperture (NA) and increasing coherence of the light source. Coherence factors include standard illumination at 250nm, annular at 90nm, and 45º quasar at 32nm, with increasing ring width per technology node. The 32nm interaction radius is actually slightly larger than the 90nm radius, and relative to pitch, is 4.5× that of the 250nm technology node.
Systematic yield monitoring requirements
Our goal for this project was to improve the manufacturing fab’s ability to understand systematic yield. To accomplish this, a daunting set of requirements had to be met:
1. The test structures needed for adequate characterization of systematic yield number into the hundreds. Key patterning layers include active, poly, and up to eight layers of metal and contact/via. Each patterning layer contains dozens of suspect systematic topologies.
2. As this infrastructure is for use in a manufacturing environment, the large group of systematic yield issues needs to be characterized in just a few minutes per wafer. A standard 9- or 13-die wafer-acceptance test plan will not be sufficient-dozens of die per wafer should be tested to see wafer spatial signatures. Longer test times would greatly limit the number of practically testable wafers, potentially limiting the ability to identify temporal, product, and process equipment yield signatures.
3. Because every product’s systematic yield will be unique, we need to fit the test structures into the kerf area of a product reticle field to allow direct monitoring of temporal or tool ID issues and to correlate resulting systematic PWs with a specific product’s yield on a specific wafer. A kerf, or scribe line, is typically 50-100µm wide, and 5-10mm of kerf length can usually be made available. Any solution using a separate mask set of test structures will be blind to these product-specific yield signatures, and will reduce profitability by requiring test wafer runs. The measurement of each systematic topology needs to be reduced to some simple but quantifiable yield metric compatible with the existing yield-improvement infrastructure. The solution should extend far beyond the test structure phase and drive the yield learning process with actionable yield metrics.
Solution description
Requirements 1 and 2 force the use of electrical test structures because any existing optical/physical inspection methods would be too slow to meet the manufacturing requirements. Requirements 1-3 can only be fulfilled by employing an addressable array design, as conventional discrete test structures passively wired to bond pads would occupy far too much area and take too long to test. (For technology development purposes, we had designed a large addressable array for both random and systematic yield analysis, and previously reported on the benefits [2]).
To fulfill requirement 3 above [3], we were able to modify this circuit to create two small addressable arrays-one each for back-end-of-line (BEOL) and front-end-of-line (FEOL) test structures-occupying kerf form factors of 90µm × 6300µm. The electrical tests in this circuit architecture are two-terminal open/short tests. This resulting array of two-terminal experiments is designed to be tested by a simple memory tester as a ROM, where the ROM array is extremely inhomogeneous, and the systematic experiments will be organized as small groups of ROM “bits.”
As discussed [2, 3], there are measurement benefits to separating FEOL and BEOL experiments, in addition to keeping the length of a complete kerf monitor circuit below 10mm given the target product die sizes. Within the constraints of a small kerf area, each of our two arrays addresses 16,000 electrical tests using 25 probe pads. This experiment density is ~100× greater than what is achievable with the highest density passive test chips. An additional benefit of this solution is the significantly shorter test time compared to passive test structures measured on parametric testers. The native measurement time of the two-terminal device and comparator is significantly less than the time taken by commercial testers to gather and write the data to disk. That is, circuit test time is tester-limited, and for the MOSAID testers we averaged 11 sec/touchdown, or ~15 min/wafer, yielding 80 die/wafer.
As mentioned above, we ultimately have to report the PW for a given systematic feature. Simply measuring the yield for a given feature may be uninformative because the yield of a feature will often be 100% for the small test structures placed in a kerf area for any reasonable wafer sampling size. Therefore, we took an “accelerating” approach to guarantee a PW measurement for every die. For each key feature, we designed a series of test structures with successively tighter design dimensions, pushing every systematic feature to a limit beyond its minimum design rule, to a point where a non-zero failure rate can be measured. This design rule acceleration must be done with care, using specific knowledge of the RET, mask data prep, and fab process behaviors and limitations.
To expand on requirement 1 above, we undertook a comprehensive review of the design rules, identifying experiments that include various printability test structures, misalignment monitors, minimum feature area test structures, OPC test structures, and special topologies to detect known systematic yield loss mechanisms. Together, the devices under test (DUT) constitute a basic suite of PW monitors for 65nm technology. Through this process, we identified 321 key systematic features on 10 key patterning levels to be monitored.
This number includes permutations of basic features. For instance, we needed to monitor metal space PWs at multiple pitches due to specific RET, lithography, and etch concerns. We also wished to monitor the PW of horizontal and vertical features separately, as the PW is astigmatic due to step-and-scan issues. To construct each systematic PW, we used, on average, 12 design variations, resulting in a total of 4080 unique experiments or DUTs. With 32,000 available tests per die, we were able to increase the robustness and reduce the noise of our data by: a) using copious reference structures with known open or short behavior, and b) placing six copies of each DUT on each die. To put this experiment set into perspective, the same number of passive experiments wired to a best-known 70µm parametric probing bond pad pitch would occupy a 12.5mm × 12.5mm square.
To handle the experimental complexity, we developed an infrastructure for this project that takes experimental variations as tabular inputs, automatically generates the 32,000 experiments in an experiment array, overlays it to the underlying two-terminal circuit architecture, and documents and organizes the PW groups in a format for direct placement into the yield management system (YMS). Human interaction in this data path would have taken an inordinate amount of time and carried an unacceptable risk of error. We created custom data analysis routines that calculate the 321 PWs for each die tested, and then store the results in the YMS system for further yield analysis.
We illustrate this overall program in Fig. 3. The complete kerf test circuit is shown in Fig. 3a. A design rule specification table listing the experiment type, location in the array, design parameters, and design values is first created, and layout experiments are generated varying the primary design parameter for this experiment.
A close-up view of the experiment array is shown in Fig. 3b, and two specific layout examples are shown in Fig. 3c. In this case, the primary design parameter is vertical misalignment of contact to active. These design values make up the x-axis of the desired systematic yield failure rate chart in Fig. 3d, while the y-axis is the failure rate, for each design permutation, for a given set of data (one die, one wafer, many wafers, etc.). The distance between 5% failure rate points is automatically extracted as the PW and is shown in the YMS charting as the horizontal green line in Fig. 3d. Additionally, the shift of this U-shaped failure rate chart around the 0 point of the x-axis is a measure of the native misalignment and is also stored as asymmetry.
For most line and space design rules, the failure rate chart will be one-sided, and the PW is the 5% failure rate x-intercept value subtracted from the minimum design rule for the technology. The system we used can receive the raw bit test results from the tester and automatically aggregate the failure signatures according to the desired PW chart, and then convert these failure statistics into die-level “PW” or “asymmetry” for each of the 321 experiment groups.
Results and application
What we accomplished in the solution summarized in Fig. 3 was to reduce a very large set of discrete test structure designs and their corresponding memory tester results into two simple parameters: PW and asymmetry. These parameters are stored in the YMS database on a per-die basis, and constitute systematic yield figures of merit for printability and misalignment, respectively. We can then use the native capabilities of the YMS to monitor process and equipment performance by reticle field, wafer, or lot, by subjecting the stored figures of merit for standard analyses such as Pareto, trend chart, statistical process control (SPC), etc. Additionally, we can correlate our systematic figures of merit to other data, such as in-line metrology data, process equipment ID, and, of course, product yield and product failure test bins.
The power of this compact systematic yield array solution is that not only can the PW be obtained initially, but any shift in the process margin from process tool-to-tool, lot-to-lot, wafer-to-wafer, and even from die-to-die within a wafer, can be also continuously monitored. In addition, any process or equipment change can be easily evaluated by comparing the appropriate PW metrics through splits. It is impossible to obtain this wide breadth or depth of information using “stand-alone” passive test structures.
Figure 4 shows an interesting case study using the layout of an experiment to measure the PW for via to bottom-metal shorts. Figure 4b shows the wafer-level PW from this experiment plotted against the corresponding wafer-average physical inter-level dielectric thickness measurement. The strong correlation between the two suggests a likely mechanism for via to bottom-metal shorts, and also helps establish the optimum target and control limits for the interlevel dielectric (ILD) thickness. With the right test structure, this information could also have been obtained by performing process split experiments, but the in situ addressable array approach saves considerable wafer cost and time associated with process splits.
 Figure 5. Wafer-level scatter plot of SRAM chip yield vs. polysilicon gate opens process window. |
In a second case, we found that the yield of the SRAM chip in the product mask set showed a strong correlation to the PW for polysilicon gate opens, as shown in Fig. 5. Below a PW of 0.055µm, the SRAM chip yield is very low. As the PW continues to increase above 0.006µm, there is a corresponding increase in the SRAM yield with the yield saturating above a PW of 0.01µm (not shown in Fig. 5), likely limited by other, random yield-loss mechanisms.
Conclusion
Monitoring 65nm systematic yield issues in a manufacturing environment involves a high degree of complexity. The solution described herein combines addressable array technology with a dedicated data reduction and analysis infrastructure compatible with an existing yield management system (e.g., Synopsys’ Odyssey YMS software). This solution is currently being used in 65nm manufacturing on multiple product mask sets, with more than 4000 unique test structures that together provide a comprehensive yet timely read-out of process and equipment performance by process module. Recent cases in which addressable array data helped detect and tackle systematic yield and variability issues prove the usefulness of these addressable arrays in a manufacturing environment.
References
- R. Haavind, “Value Creation While Maximizing Return on Capital,” Solid State Technology, Vol. 50, Issue 1, January 2007.
- M. Karthikeyan, S. Fox, W. Cote, G. Yeric, M. Hall, J. Garcia, et al., “A 65nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array with Integrated Analysis Software,” Proc. 2006 Int’l Conf. Microelectronic Test Structures (ICMTS 2006), IEEE Press, pp. 104-109.
- M. Karthikeyan, A. Gasasira, S. Fox, G. Yeric, M. Hall, J. Garcia, et al., “Development and Use of Small Addressable Arrays for Process Window Monitoring in 65nm Technology,” Proc. 2007 Int’l Conf. Microelectronic Test Structures (ICMTS), March 2007.
Greg Yeric received his BS, MS, and PhD degrees in electrical engineering from the U. of Texas at Austin, US. Previously, he was chief technologist at HPL Technologies. Yeric is a DFM technologist at Synopsys, 1301 South Mopac Expressway, Bldg 4, Suite 200, Austin, TX, 78746, United States; ph 512/372-7500, e-mail [email protected].
Muthu Karthikeyan received his PhD in chemical engineering from Rensselaer Polytechnic Institute, Troy, NY, in 1997. He worked for WaferTech prior to joining IBM in 2003. He is a senior engineer at IBM Microelectronics, Hopewell Junction, NY, United States.
Stephen Fox received his BSc in experimental physics from the U. of York, UK, in 1987. He manages the inline defectivity team for development technologies in IBM’s East Fishkill 300mm fab, Hopewell Junction, NY, United States.