Technology news
08/01/2007
Intel promotes computation lithography capabilities
Intel typically uses its annual “Research Day” to disclose potential commercial applications of its technologies, but the event held June 20 also contained a demonstration of the way Intel’s technology advances the chipmaker’s own electronics manufacturing. The company showed how “computational lithography,” which leverages improvement in computation to facilitate manufacturing innovations that maintain Moore’s Law, will be the backbone of Intel’s proprietary DFM strategy for the foreseeable future.
In the application described by Vivek Singh, manager of Intel’s lithography modeling group and Yan Borodovsky, senior fellow and director of advanced manufacturing lithography, the desired chip pattern is inverted mathematically using Maxwell’s equations to define the photomask geometry that best projects that image. Going beyond optical proximity correction (OPC) and design rules, Intel’s modeling technology allows chips to be built using equipment that is nominally one generation behind. That, in turn, lowers costs and accelerates progress by permitting the use of existing tools. In the case of critical layers for 45nm logic, the use of dry lithography instead of immersion lithography at 193nm lowered costs by 27%, according to Borodovsky.
Computational lithography does require resources, however. The computational lithography and DFM group at Intel comprises 40 people. Mike Mayberry, VP and director of components research, admitted that the early full-chip simulations required a million CPU hours, though since then the EMF inversions have gotten “more efficient.” Once the design converges, actual geometries have to be fabricated on photomasks, and then inspected and repaired. Borodovsky pointed out the advantages of having all those functions at a single corporation-an IDM, not a fab-lite company, or a fabless-maskmaker-foundry alliance.
In a tour-de-force of computational lithography, Borodovsky also revealed the successful fabrication of 65nm Cedarmill chips in 2006 with the first metal layer printed using a pixelated phase mask. In a pixelated PSM, arrays of sub resolution pits are etched into the fused silica substrate in a grid pattern that projects the desired image, as optimized by the inversion computation. The actual mask pattern (see Figure, panel b) bears little resemblance to the design (panel a) but nevertheless results in the desired photoresist pattern (panel c).
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Doing this on a full-chip with yield comparable to the control wafers in the split lot is a signal accomplishment. Among other challenges are those of etching all the pits (whatever their size) to the same phase shift, inspecting the resulting mask and repairing defects (eight were found, according to Borodovsky). Since the mask structure is so much more complex than the final image, a unique aerial image inspection system must be employed for the full-field mask. The resulting pattern with k1=0.29 approaches the k1=0.25 single exposure limit more closely than other logic-chip reports.
While Intel did not find it necessary to adopt pixelated mask technology for 65nm or 45nm, and does not expect it to be needed for 32nm, Borodovsky commented that it remains an option for 22nm if more mainstream technologies (such as EUV and double patterning) experience delays. And both Borodovsky and Singh asserted that computational lithography will be the backbone of Intel’s proprietary DFM strategy for the foreseeable future. -M.D.L.
Applied’s new mask etcher carves a niche at 45nm
As use of aggressive OPC proliferates on masks for 45nm manufacturing and beyond, etch requirements for CD uniformity (CDU) and CD bias are becoming more stringent and applying to more chip levels. Addressing the requirements on CDU, etch bias, linearity, as well as defectivity for etching the diverse materials (chrome, quartz, and MoSi) on masks at advanced nodes, is Applied Materials’ latest mask etcher, the Centura Tetra III Advanced Reticle Etch.
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Masks are rarely identical, but any maskmaking tool must produce the intended geometries reliably no matter what they are or where they are on the substrate. With some sub-resolution features on today’s masks only 100nm in width, any substantial lateral resist erosion or etch bias between the initial resist and final chrome (or MoSi) dimensions is unacceptable, as is global CD nonuniformity due to plasma effects or microloading.
 Figure 2. Chrome CD linearity performance. (Source: Applied Materials) |
Loading performance at 45nm-i.e., getting the same low CD bias everywhere on the mask, for all features/all sizes-is perhaps the most challenging requirement for mask etchers. Thus, the near zero linearity (CDU <3nm 3σ) through pitch and duty factor is a key advantage of the Tetra III, according to Ibrahim M. Ibrahim, GM of Applied’s mask etch division. “The level of CD control is consistent across all features and various duties or global loads and pattern layout symmetries (Fig. 1),” he said. “At <3nm CD linearity, the new tool exceeds the ITRS roadmap requirement for 2010 by more than 50% (Fig. 2),” he pointed out, adding that this microloading performance has been achieved for feature sizes ≤100nm.
 Figure 3. Phase uniformity of APSM mask. (Source: Applied Materials) |
Trench depth is critical for quartz etch on alternating PSMs. The Tetra III incorporates controls on coil adjustment, and the multiport gas injection system permits a trench depth uniformity corresponding to <2˚ phase range at all times, with minimum development effort, according to Ibrahim. Trenches corresponding to the desired phase shift angles (typically 180°) have straight profiles (>87˚) and smooth surfaces with no quartz roughness, he pointed out. “The Cr:MoSi stacks on PSMs can be etched in an integrated/combo process, with the resist intact, reducing any risk of defects and increasing productivity, while maintaining a <2˚ phase range and minimal microtrenching of the substrate (Fig. 3),” Ibrahim noted.
Based on Applied’s Etch Centura AP mainframe, the Tetra III can house up to four chambers in a cluster formation-e.g., chrome, MoSi, quartz, and a backup chamber for R&D work. Three different end-point detection modes (optical emission, interferometry, and transmission) can be utilized, in the same recipe if necessary. The etcher can also be used for R&D activities to etch EUV masks. -D.V.
IITC 2007: Airgaps and chip-stacks
Airgaps and 3D-stacks were the big news from the 10th International Interconnect Technology Conference (IITC, June 4-6, San Francisco, CA). Aside from two major presentions-IBM showed rhodium (Rh) electro-chemical deposition (ECD) for ≤32nm contact plugs, and Fujitsu showed nano-clustered silicon (NCS) with low k=2.25 for a dielectric-most new work involves the same materials combined in clever new ways.
Airgap technology was covered in four oral presentations, three posters, and countless informal hallway discussions. Dan Edelstein, IBM Fellow and manager of BEOL technology strategy at Yorktown Heights, NY, gave an invited talk on the many integration challenges for 32nm node interconnects, including resist poisoning from low-k outgassing, low-k damage removal, and the need for improved thin-film interfaces. “We need to keep adding innovation just to stay on the trend-line,” he commented. For example, the industry has historically seen chronically low SiCOH low-k adhesion on SiCHN barrier layers-regardless of equipment, CVD precursor, or plasma preclean-due to a carbon-rich initial deposition. Adding a diverter-valve to the tool allows for stabilized precursor flow before RF power is turned on, which eliminates the carbon-rich deposition and thus solves the adhesion issue.
With such subtle integration challenges, IBM has chosen to add airgaps as a side-loop with no new materials, tools, or baseline processes. Airgaps drop k by ~35% for any given dielectric material, Edelstein noted, adding that IBM has “shown this on gapped SiOF and low-k SiCOH, and will do it next on ULK porous SiCOH.” The IBM airgap process both removes and re-deposits some dielectric material, while most airgap approaches for logic chips rely on removal processes alone.
The Crolles2Alliance (CEA-Leti, Freescale, NXP, and ST) also showed some of the integration tricks needed to use porous ULK dielectrics at the 32nm node. Different plasmas may seal pore surfaces to provide barrier properties for long-term reliability: CH4 adds C, NH3 substitutes N for C leading toward SiON compositions, and He/H2 plasmas retain near original stoichiometry. Though Cu bulk resistivity is only ~2.2 µOhm-cm, for 60nm line widths, it is ~2.9 and increases with reducing widths. CMOS32 uses 50nm Cu line widths for M1, requiring a self-aligned barrier <4nm for EM performance, an ALD barrier and thin-Cu seed for filling, and either a CuSiN or CoWP cap layer.
NEC research labs showed that direct ECD of Cu without a Cu-seed layer provides larger grain size and higher Cu(111) orientation. Damascene structures were first sealed with TiN, then either Ta/Cu or Ru layers were deposited. The TiN barrier layer is definitely needed beneath Ru to block Cu diffusion into the dielectric. Ru PVD using DC magnetron sputtering with Ar gas at room temperature produces high orientation of Ru(002). Since Ru(002) is hexagonal-close-packed, it matches well with the preferred Cu(111) face-centered-cubic orientation such that 40%-50% can be grown directly on Ru in dual-damascene structures. Some day, metal line specifications may include not just dimensions and resistivity, but grain orientation and size-distribution, too.
Ibaraki U. and Hitachi presented research showing that higher chemical purity leads to lower resistivity in Cu lines. Increasing both the Cu anode purity from 4N to 9N along with the CuSO45H2O purity from 3N to 6N reduced line resistance by 21% in 50nm wide lines, with all other process parameters held constant. The high-purity process increased the average grain size from 70 to 74nm, and significantly reduced the oxygen content in the final annealed Cu lines to <1 wt% from the previous 3-4 wt%.
Based on first principles of thermodynamics, an alloy of Cu/Mn can be annealed to result in self-segregation of Mn to the dielectric/Cu barrier. One fundamental advantage of this process is that no barrier is formed at the bottoms of vias, which minimizes resistance. Toshiba’s R&D group tested self-aligned Mn barriers with 244-via-chain structures and found one-third the resistance compared to Cu vias using the standard Ta barrier. -E.K.
See the full text of this report at sst.pennnet.com.