Will RDRs lead to a resurgence of in-house design tools?
08/01/2007
In many ways, it was a lot easier in the 1960s and 1970s, before disaggregation. Integrated device manufacturers (IDMs) had ownership of all the technologies that were needed to design and manufacture integrated circuits: device and process R&D, semiconductor equipment, and IC design tools. In the 1980s, it became apparent that we needed to outsource work to companies that were specialists in these technologies. First to go was semiconductor equipment, followed by IC design tools. This approach worked well through the 1990s, as the problems could be solved by incremental advances in the technologies-this was the “cream-puff era” of semiconductors.
Unfortunately, the new century brought us back to reality with basic research issues not seen since the 1980s. The first one to hit was the failure of the semiconductor equipment vendors to produce subwavelength lithography. Technologies started to collide. Semiconductor equipment manufacturers started balking at the high cost of R&D that had no guarantee of producing revenue. After all, when they couldn’t produce an economical UV stepper, the EDA industry came forward and solved the problem with OPC software. One semiconductor vendor even teamed with an EDA vendor on a design for manufacturing (DFM) R&D program, although they called off the effort two years later because the semiconductor equipment vendors solved the problem first.
That brings us to device and process R&D: one approach to any semiconductor manufacturing problem is to fix the silicon itself. As we approached 65nm silicon, some of the IDMs noticed that there were far fewer DFM issues with regular structures such as memory and field-programmable gate arrays (FPGAs). This led to research into structured regular silicon fabrics, which IBM called RDR (restricted design rules). RDRs could have a big impact not only on the DFM market, but on the IC layout market as well. Things get much easier when you move to RDR silicon, and we are moving in that direction. All of the 45nm processes have adopted some restricted design rules. The real test will be at 32nm.
Even more exciting, we are seeing a major exodus of silicon manufacturers from product and process R&D, especially with respect to research. We don’t know when it will stop, but it appears that the number of companies or consortia that will continue funding their silicon process research may be, at best, six, or, at worst, only two.
One of the problems with FPGAs is that they all are different. You can’t use a standard tool to place and route any of the different vendors’ products; you need fitters that today are all developed in-house at the FPGA vendor. This situation has kept the FPGA vendors from outsourcing their design tools to the EDA vendors. A few tools-very few-are supplied by the EDA community and thus the FPGA tool market has remained small compared to the ASIC tool market.
The question is, if there are only a few processes being developed, and they begin using more of the RDRs, will they all be sufficiently different that you can no longer build standard EDA tools that are optimal, or do you need to target each process separately? And if this is the case, are the companies and consortia that do the silicon research going to bring the design tool R&D back in-house? Probably not, but it will be tempting.
Contact Gary Smith, chief analyst, Gary Smith EDA, PO Box 2990, Santa Clara, CA 95055; ph 408/985-2929, e-mail [email protected], www.garysmitheda.com.
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Gary Smith, Gary Smith EDA, Santa Clara, California