Issue



Quantifying ALD technologies for high aspect ratio structures


08/01/2007







Chemical vapor deposition (CVD) has become an essential technique for thin film deposition in integrated circuits (IC). Generally, complicated deposition processes are described using multipath and multistep reaction schemes, including parameters to account for mass-transport processes, the gas-phase formation of intermediates, surface reactions, adsorption and desorption processes, etc. The best thin film thickness uniformity and film quality can be achieved when CVD processes are realized at conditions where the whole process is limited by a surface reaction.

ALD has recently become very popular for semiconductor applications since its chemisorption-based surface limiting reactions are strongly dominant. ALD processes are not dependent on mass-transport phenomena, and should provide an inherent monolayer deposition and 100% step-coverage in high aspect-ratio (AR) gaps. Recently published data confirm that ALD provides good step coverage of deposited thin films at the top, middle, and bottom area of narrow and deep gaps [1].

However, the industry’s accumulated CVD experience teaches us that any thin film technique that seems perfect when applied to a flat surface (a “blanket deposition”) reveals some issues and limits with stepped device structures. Deposition issues over severe topography can be considered in terms of specific parameters such as: thin film conformality, seams, voiding phenomenon, gap-fill, step height (H), gap (G), aspect ratio (AR = H/G), etc.

Traditionally, to characterize the capability of a certain deposition technique to cover stepped IC structures, a set of step coverage or gap-fill studies are performed using test structures with pre-defined gap sizes and AR values. However, additional factors must be considered for proper quantification of the process capability-including gap shape and sidewall slope. Also, since the AR continues to increase as per the International Technology Roadmap for Semiconductors (ITRS) [2, 3], it is reasonable to consider that ALD may not be “a priori” perfect for extremely narrow and deep gap applications. We have shown a methodology for quantification of ALD processes and thin film growth in narrow gaps.

ALD related to CVD

ALD can be considered to be just a certain extreme case of CVD. There are not too many differences between CVD and ALD in apparatus, precursors, or general deposition methodology. ALD intentionally uses consecutive short-pulsing precursor injections into the reaction chamber, and the substrate is typically heated to a lower temperature than in “traditional” CVD processes.


Figure 1. Positioning of ALD among other deposition techniques using step coverage vs. K(r)eff data on a logarithmic scale.
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To help define ALD among the other known CVD methods, we can invoke the previously defined parameter of “an effective constant of the deposition rate” (K(r)eff) [4-6], in terms of the thickness deposited over time (cm/sec). This experimentally obtained and simplified reaction parameter describes all studied CVD reactions as first-order with respect to the main thin film reaction component, because the others are normally used in significant excess. Compared to the “deposition rate,” which depends on the chamber design and process conditions, K(r)eff values correlate with step coverage values (Fig. 1) [5] for most studied CVD methods such as TEOS-based and silane-based atmospheric pressure (APCVD), sub-atmospheric pressure (SACVD), low pressure (LPCVD), plasma enhanced (PECVD), and high-density plasma (HDP-CVD), as well as thin films of silicon dioxide and glasses, poly, nitride, etc.

Based on common ALD process conditions, we estimate a K(r)eff range of about 0.01-0.05 cm/sec. This is a much lower range than that of CVD processes. Using this ALD K(r)eff range and commonly adopted 100% film conformality, ALD falls into a logical sequence with studied CVD processes (Fig. 1).

The table summarizes the deposition parameters found with extreme cases of low and high K(r)eff. It is clear that for low K(r)eff ALD, some disadvantages include low reaction efficiency (just a few % precursors used) and subsequent wasting of expensive precursors [7].

Gap deposition with “structure complexity”

Systematic studies on void-free gap-fill capability of pre-metal dielectric films deposited by CVD techniques [8, 9] included an analysis of a number of scanning electron microscopy (SEM) cross-sections to look for voids in gaps with vertical, tapered, and re-entrant sidewalls. Defining a “structure complexity” (SC) parameter for gaps with vertical shape as the ratio of the AR to the gap size (1/µm) allows for correlation of void-free film step coverage in deposition reactions.


Figure 2. Structure complexity values for the 2005 ITRS and for some best known method gap-fill CVD processes.
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Hence, by analyzing the voiding appearance in IC structures using a SEM technique, one can easily define the critical values of the SC for the structure that could be successfully filled with a certain CVD technique or process (Fig. 2). The SC parameter for silicon dioxide TEOS-based LPCVD process and un-doped TEOS-ozone based silicon dioxide APCVD and SACVD processes is ~10. Typical silicon dioxide HDP-CVD processes have a parameter of ~20.

Extension of process capability can be expressed as greater SC factor. For example, adding isotropic etching precursors such as halogens to HDP-CVD [10] reduces vertical non-uniformity of the film deposited by RF bias sputtering. The latest reports [11, 12] describe modifications of HDP-CVD to improve gap-fill capabilities. HDP-CVD gap-filling of STI trenches with 90nm gaps and AR ~6 were done using NF3 gas added to the silane-oxygen mixture under low process pressure condition [13] to reach parameters of ~40 and ~66 (Fig. 2).


Figure 3. Calculated changes of structure complexity and aspect ratio (AR) with the gap shrink during thin film growth in the gap.
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Data in Fig. 2 present just certain “starting values” of AR and SC, while numbers will drastically increase along with shortening of the gap size (Fig. 3). Gap size shrink and nonconformal film deposition cause the voiding phenomenon.

Thin film ALD in narrow gaps

This characterization methodology can help develop high AR gap ALD. The use of device structures with a set of vertical gaps having different depths and gap sizes allows for the evaluation of the SC values.


Figure 4. Experimental data for step coverage capability of the different CVD and ALD techniques. Data for “modified” HDP-CVD are presented assuming that void-free gap-fill provides conformal film step coverage.
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One use of ALD is for the growth of relatively thin films, which cover just gap side walls and gap bottom. Step coverage calculations can be made using measurements from some pre-determined gap areas in standard SEM cross-sections (Fig. 4). A CVD ruthenium film [14] shows decrease of step coverage with SC increase, while ruthenium ALD provides conformal step coverage at the optimized process conditions [15]. Structures with complexity values from 50 to 100 have been 100% covered by WN, ZrO2, and HfO2 films [16].

Click here to enlarge image

Analysis of step coverage in deep trenches is typically complicated by the top film boundary inside the gap being difficult to see. We propose a second technique beyond step-coverage analysis: intentional voiding to quantify gap-fill capability. For a gap with vertical side walls, a void after deposition is a consequence of non-conformal thin film growth. Because voids should not appear if a thin film is deposited with 100% step coverage, the presence of void in the gap is clear evidence that the step coverage is not conformal. Assuming that optimized experimental conditions for conformal films are employed, one can simply attempt to completely fill a set of vertical holes with different depths and gaps. Following sample preparation for routine SEM cross-section, analysis should include an additional “decorative” etch step to highlight the boundaries of film to more accurately measure gap size, gap depth, and SC. In this way, thin film conformality for given structures can be quantified (Fig. 4). This second analysis method may appear to be slightly artificial, but it provides useful information and can be used to double-check step coverage tests.

Summary

Experimental procedures can be simplified by selecting proper structures for ALD process and tool characterization. Both quantitative step coverage and intentional voiding could be used to determine the ALD capability for conformal film deposition. Both can assist in thorough comparisons between single and batch ALD tools, and evaluating the capabilities of different ALD techniques.

Characterization of the ALD technique is supposed to depend not only on the given gap size but also on the SC values. Deeper structures with a little bit wider gap size, but with equal SC values, can thus presumably be adequate choices for advanced process characterization.

References

  1. D. Vogler, P. Doe, “ALD Special Report: Where’s the metal?” Solid State Technology, p. 35, Jan. 2003.
  2. International Technology Roadmap for Semiconductors, 2001.
  3. International Technology Roadmap for Semiconductors, 2005.
  4. V.Y. Vassiliev, “Kinetics and Mechanism of CVD Reactions of Silicon-based Thin Films,” 197th Electrochemical Society Meeting Volume, Abstract #884, May 14-18, 2000.
  5. V.Y. Vassiliev, “Relationships between Gas-phase Film Deposition, Properties and Structures of SiO2 and BPSG Films,” J. Electrochem. Soc., 150(12), p. F211-F218, 2003.
  6. V.Y. Vassiliev, S.M. Repinsky, “Chemical Vapor Deposition of Thin Film Dielectrics,” Russian Chemical Reviews, 74(5), pp. 413-441, 2005.
  7. C. Bailey, K. Hutchison, M. Wilders, “Vacuum Systems for ALD,” Solid State Technology, p. 30, October 2006.
  8. V.Y. Vassiliev, “Void-free Pre-Metal Gap-Fill Capability of CVD Films for Subquarter Micron ULSI,” Proc. of 6th Intern. Dielectric for ULSI Multilevel Interconnection Conference (DUMIC), Santa Clara, p. 121, 2000.
  9. V.Y. Vassiliev, J.L. Sudijono, A. Cuthbertson, “Trends in Void-free Pre-Metal CVD Dielectrics,” Solid State Technology, p. 129, March 2001.
  10. V.Y. Vassiliev, J.L. Sudijono, Y. Pradeep, J. Yu, US Patent 6355581, 2002.
  11. B. Geoffrion, A. Patel., S. Kim, et al. “New HDP-CVD Technology for Next-generation Gap Fill Processes,” Semiconductor Fabtech, N15, p. 191, February 2005.
  12. H. Nishimura, S. Takagi, M. Fujino, N. Nishi, “Gap-fill Process of Shallow Trench Isolation for 0.13µm Technologies,” Jpn. J. Appl. Phys., V. 41, Part 1, N. 5A, p. 2886, 2002.
  13. J. Radecker, H. Weber, “Extending the HDP-CVD Technology to the 90nm Node and Beyond with an In situ Etch Assisted (ISEA) HDP-CVD Process,” Proceedings of 2003 IEEE/SEMI Advanced Manufacturing Conference, p. 125.
  14. S.-K. Won, W.-D. Kim, C.Y. Yoo, et al., “Conformal CVD-Ruthenium Process for MIM Capacitor in Giga-bit DRAMs,” 2000 IEDM Tech. Dig., pp. 789-792.
  15. C. Manke, O. Boissiere, U. Weber, et al. “Growth of Ru/RuO2 Layers with Atomic Layer Deposition on Plain Wafers and into Trench Structures,” Microelectron. Eng., 83, pp. 2277-2281, 2006.
  16. O. Sneh, R.B. Clark-Phels, A.R. Londergan, et al. “Thin-film Atomic Layer Deposition Equipment for Semiconductor Processing,” Thin Solid Films, 402, pp. 248-261, 2002.

Vladislav Vasilyev received his MS in chemistry from Novosibirsk State U., Russia, in 1976, and his PhD in physical chemistry and DSc in solid state chemistry from the Russian Academy of Sciences in 1990 and 2002, respectively. He is an invited professor at Korea Polytechnic University, 2121, Jeongwang-Dong, Shiheung-City, Kyungki-Do, 429-793, Korea; ph 82/31-8041-1326, e-mail [email protected].

Sung-Hoon Chung received his MSc and PhD in electronic materials engineering from Kwangwoon U., South Korea, and his PhD in electronic systems engineering from the U. of Essex, England, in 1993, 1998, and 2005, respectively. He is an adjunct professor in the department of nano-optics engineering of Korea Polytechnic U.

Yong Won Song received his MSc in materials engineering from Korea U., South Korea, and his PhD in physics from Moscow State U., Russia in 1988 and 1995, respectively. He is a vice professor in the department of nano-optics engineering at Korea Polytechnic U.